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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 19541 occurrences of 5230 keywords
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Results
Found 53773 publication records. Showing 53773 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
62 | Grant Martin |
Verification by the pound. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(5), pp. 478-479, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
complex ICs, verification methodologies, hardware verification languages, formal verification, functional verification, dynamic verification |
57 | Pradip A. Thaker |
Holistic verification: myth or magic bullet? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 204-208, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SoC verification, mixed-signal verification, power management verification, emulation |
50 | David Cyrluk, Mandayam K. Srivas |
Theorem proving: not an esoteric diversion, but the unifying framework for industrial verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 538-544, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
industrial hardware verification, industrial verification, formal verification, logic testing, theorem proving, theorem prover, hardware verification |
49 | Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan |
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 11-13, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
48 | Subrat Kumar Panda, Arnab Roy 0001, P. P. Chakrabarti 0001, Rajeev Kumar 0004 |
Simulation-based verification using Temporally Attributed Boolean Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(4), pp. 63:1-63:52, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bus verification, instruction semantics verification, interrupt testing, offline-online verification algorithm, simulation based verification, temporal logic, timing verification |
48 | Elliot Barlas, Tevfik Bultan |
Netstub: a framework for verification of distributed java applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASE ![In: 22nd IEEE/ACM International Conference on Automated Software Engineering (ASE 2007), November 5-9, 2007, Atlanta, Georgia, USA, pp. 24-33, 2007, ACM, 978-1-59593-882-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
testing and verification of, model checking, automated verification |
48 | Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso |
Is methodology the highway out of verification hell? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 521-522, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
verification, formal verification, methodology, assertions |
48 | Daniel Jackson 0001 |
Hazards of Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 1, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Brigitte Wirtz |
Average prototypes for stroke-based signature verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: 4th International Conference Document Analysis and Recognition (ICDAR '97), 2-Volume Set, August 18-20, 1997, Ulm, Germany, Proceedings, pp. 268-272, 1997, IEEE Computer Society, 0-8186-7898-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
stroke-based signature verification, average prototypes, enrolment subsystem, verification subsystem, reference construction, verification rates, position-based averaging, time-based averaging, representative input signatures, varying stroke structures, missing strokes, additional strokes, natural stroke structure, input signatures, handwriting recognition, error rate, dynamic signature verification |
46 | Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang |
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 327-332, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
verification strategy, optimization, functional verification, coverage analysis, hierarchical verification |
46 | Tevfik Bultan, Aysu Betin-Can |
Scalable Software Model Checking Using Design for Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VSTTE ![In: Verified Software: Theories, Tools, Experiments, First IFIP TC 2/WG 2.3 Conference, VSTTE 2005, Zurich, Switzerland, October 10-13, 2005, Revised Selected Papers and Discussions, pp. 337-346, 2005, Springer, 978-3-540-69147-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Pao-Ann Hsiung, Farn Wang, Ruey-Cheng Chen |
On the verification of Wireless Transaction Protocol using SGM and RED. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 379-383, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Wireless Transaction Protocol verification, SGM, process concurrency, clock variables, discrete variables, intelligent permutation, explosion factors, scalable verification, State-Graph Manipulators, world standard, large clock constants, large discrete constants, Region Encoding Diagram, state-space size explosions, WTP verification, real time systems, protocols, data structures, data structures, formal verification, formal verification, mobile communication, Wireless Application Protocol, state spaces, RED, state-space methods, reduction techniques |
44 | Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller |
Emulation verification of the Motorola 68060. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 150-158, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level |
43 | Ryan B. Bond, Curtis C. Ober, Patrick M. Knupp |
Measuring progress in Premo order-verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Eng. Comput. ![In: Eng. Comput. 23(4), pp. 283-294, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Sergey V. Polyakov, Assaf Schuster |
Verification of the Java Causality Requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software Verification and Testing, First International Haifa Verification Conference, Haifa, Israel, November 13-16, 2005, Revised Selected Papers, pp. 224-246, 2005, Springer, 3-540-32604-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Java, Verification, Complexity, Concurrency, Shared Memory, Multithreading, Memory Model |
43 | Harry Foster |
Assertion-Based Verification: Industry Myths to Realities (Invited Tutorial). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings, pp. 5-10, 2008, Springer, 978-3-540-70543-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Simulation, Formal Verification, Debugging, Assertion, Functional Verification, Property Specification, Assertion-Based Verification |
43 | Shady Copty, Itai Jaeger, Yoav Katz |
Path-Based System Level Stimuli Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software Verification and Testing, First International Haifa Verification Conference, Haifa, Israel, November 13-16, 2005, Revised Selected Papers, pp. 1-13, 2005, Springer, 3-540-32604-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Chien-Ju Ho, Kuan-Ta Chen |
On formal models for social verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KDD Workshop on Human Computation ![In: Proceedings of the ACM SIGKDD Workshop on Human Computation, Paris, France, June 28, 2009, pp. 62-69, 2009, ACM, 978-1-60558-672-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Amazon Mechanical Turk, sequential verification, simultaneous verification, game theory, human computation, games with a purpose |
42 | Milind Kulkarni 0003, J. Benita Bommi |
Assertion-Based Verification for the SpaceCAKE Multiprocessor - A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software Verification and Testing, First International Haifa Verification Conference, Haifa, Israel, November 13-16, 2005, Revised Selected Papers, pp. 43-55, 2005, Springer, 3-540-32604-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Kun Peng, Feng Bao 0001 |
Batch ZK Proof and Verification of OR Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inscrypt ![In: Information Security and Cryptology, 4th International Conference, Inscrypt 2008, Beijing, China, December 14-17, 2008, Revised Selected Papers, pp. 141-156, 2008, Springer, 978-3-642-01439-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Batch proof and verification, knowledge statements linked with OR logic |
42 | Wei Wu 0001, Yi Mu 0001, Willy Susilo, Xinyi Huang 0001 |
Server-Aided Verification Signatures: Definitions and New Constructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ProvSec ![In: Provable Security, Second International Conference, ProvSec 2008, Shanghai, China, October 30 - November 1, 2008. Proceedings, pp. 141-155, 2008, Springer, 978-3-540-88732-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Server-aided computation, server-aided verification, BLS, ZSS, untrusted server, random oracle |
40 | Maria C. Yuang, Aaron Kershenbaum |
Parallel Protocol Verification: The Two-Phase Algorithm and Complexity Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Automatic Verification Methods for Finite State Systems ![In: Automatic Verification Methods for Finite State Systems, International Workshop, Grenoble, France, June 12-14, 1989, Proceedings, pp. 303-316, 1989, Springer, 3-540-52148-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
40 | Shmuel Ur |
A Panel: Unpaved Road Between Hardware Verification and Software Testing Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software, Verification and Testing, Second International Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, 2006. Revised Selected Papers, pp. 122-123, 2006, Springer, 978-3-540-70888-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Aarti Gupta |
From Hardware Verification to Software Verification: Re-use and Re-learn. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 14-15, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Armen Kostanyan, Vardan Matevosyan, Samvel K. Shoukourian, Anna Varosyan |
An approach for formal verification of business processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SpringSim ![In: Proceedings of the 2009 Spring Simulation Multiconference, SpringSim 2009, San Diego, California, USA, March 22-27, 2009, 2009, SCS/ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cycle transformation, formal verification, business process |
39 | Hana Chockler, Orna Kupferman, Moshe Y. Vardi |
Coverage metrics for formal verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 8(4-5), pp. 373-386, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Algorithms, Model checking, Formal verification, Coverage metrics |
38 | Haiyan Xiong, Paul Curzon, Sofiène Tahar, Ann Blandford |
Formally Linking MDG and HOL Based on a Verified MDG System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFM ![In: Integrated Formal Methods, Third International Conference, IFM 2002, Turku, Finland, May 15-18, 2002, Proceedings, pp. 205-224, 2002, Springer, 3-540-43703-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
hybrid verification systems, deductive theorem proving, symbolic state enumeration, usability verification, hardware verification |
38 | Ahmed Bouajjani, Peter Habermehl, Tomás Vojnar |
Verification of parametric concurrent systems with prioritised FIFO resource management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 32(2), pp. 129-172, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Parameterised verification, Infinite-state system verification, Cut off, Parameterised networks of processes, Model checking, Formal verification, Resource sharing |
38 | Balkhis Abu Bakar, Tomasz Janowski |
Automated Result Verification with AWK. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 6th International Conference on Engineering of Complex Computer Systems (ICECCS 2000), 11-15 September 2000, Tokyo, Japan, pp. 188-, 2000, IEEE Computer Society, 0-7695-0583-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
AWK, result-based specifications, formal specification, formal verification, specification, software components, error detection, program generators, result-verification, result verification |
38 | Valeria Bertacco |
Low maintenance verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 12, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Hana Chockler, Orna Kupferman, Moshe Y. Vardi |
Coverage Metrics for Formal Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings, pp. 111-125, 2003, Springer, 3-540-20363-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | John M. Rushby, Friedrich W. von Henke |
Formal Verification of Algorithms for Critical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 19(1), pp. 13-23, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
machine-checked verification, Byzantine fault-tolerant algorithm, digital flight control system, fault-tolerant synchronization, EHDM system, formal specification, formal specification, formal verification, fault tolerant computing, software reliability, safety, synchronisation, critical systems |
37 | Domagoj Babic, Alan J. Hu |
Exploiting Shared Structure in Software Verification Conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 169-184, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Satoshi Yamane |
The verification technique of real-time systems using probabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: Third International Workshop on Real-Time Computing Systems Application (RTCSA '96), October 30 - November 01, 1996, Seoul, Korea, pp. 90-97, 1996, IEEE Computer Society, 0-8186-7626-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
performance properties, dense time model, dense time statecharts, automatic verification method, dense time model checking, real-time systems, reliability, formal specification, formal verification, formal verification, temporal logic, probabilities, verification technique |
36 | Ajay J. Daga, William P. Birmingham |
A symbolic-simulation approach to the timing verification of interacting FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 584-589, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
symbolic-simulation approach, interacting FSMs, timing verifier, complex sequential circuit verification, combinational paths, inherently modular nature, symbolic simulation verification methodology, formal verification, logic testing, finite state machines, finite state machines, sequential circuits, circuit analysis computing, timing verification |
36 | Naoki Kobayashi 0001, Naoshi Tabuchi, Hiroshi Unno 0001 |
Higher-order multi-parameter tree transducers and recursion schemes for program verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Proceedings of the 37th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2010, Madrid, Spain, January 17-23, 2010, pp. 495-508, 2010, ACM, 978-1-60558-479-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
higher-order tree transducers, tree-processing programs, program verification, higher-order recursion scheme |
36 | Hua Yan, Wei Zhang 0004, Haiyan Zhao, Hong Mei 0001 |
An Optimization Strategy to Feature Models' Verification by Eliminating Verification-Irrelevant Features and Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSR ![In: Formal Foundations of Reuse and Domain Engineering, 11th International Conference on Software Reuse, ICSR 2009, Falls Church, VA, USA, September 27-30, 2009. Proceedings, pp. 65-75, 2009, Springer, 978-3-642-04210-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Problem size, Verification, Reduction, Feature model |
35 | Robert Beers |
Pre-RTL formal verification: an intel experience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 806-811, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
TLC, explicit state enumeration, microarchitecture verification, formal verification, protocol verification, TLA+ |
35 | Michael Abd-El-Malek, Gregory R. Ganger, Michael K. Reiter, Jay J. Wylie, Garth R. Goodson |
Lazy Verification in Fault-Tolerant Distributed Storage Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SRDS ![In: 24th IEEE Symposium on Reliable Distributed Systems (SRDS 2005),26-28 October 2005, Orlando, FL, USA, pp. 179-190, 2005, IEEE Computer Society, 0-7695-2463-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Ann E. Kelley Sobel, Richard C. Linger |
Advances in Software Specification and Verification - Minitrack Introduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 34th Annual Hawaii International Conference on System Sciences (HICSS-34), January 3-6, 2001, Maui, Hawaii, USA, 2001, IEEE Computer Society, 0-7695-0981-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Prabhat Jain, Prabhakar Kudva, Ganesh Gopalakrishnan |
Towards a Verification Technique for Large Synchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, Fourth International Workshop, CAV '92, Montreal, Canada, June 29 - July 1, 1992, Proceedings, pp. 109-122, 1992, Springer, 3-540-56496-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
35 | Eran Yahav, G. Ramalingam |
Verifying safety properties using separation and heterogeneous abstractions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation 2004, Washington, DC, USA, June 9-11, 2004, pp. 25-34, 2004, ACM, 1-58113-807-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
typestate verification, verification, program analysis, abstract interpretation, safety properties |
34 | Alan J. Hu |
Simulation vs. Formal: Absorb What Is Useful; Reject What Is Useless. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 1-7, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Sharad Malik |
A Case for Runtime Validation of Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software Verification and Testing, First International Haifa Verification Conference, Haifa, Israel, November 13-16, 2005, Revised Selected Papers, pp. 30-42, 2005, Springer, 3-540-32604-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Amir Pnueli, Tamarah Arons |
TLPVS: A PVS-Based LTL Verification System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Verification: Theory and Practice ![In: Verification: Theory and Practice, Essays Dedicated to Zohar Manna on the Occasion of His 64th Birthday, pp. 598-625, 2003, Springer, 3-540-21002-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Susanne Graf, Jean-Luc Richier, Carlos Rodriguez, Jacques Voiron |
What are the Limits of Model Checking Methods for the Verification of Real Life Protocols? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Automatic Verification Methods for Finite State Systems ![In: Automatic Verification Methods for Finite State Systems, International Workshop, Grenoble, France, June 12-14, 1989, Proceedings, pp. 275-285, 1989, Springer, 3-540-52148-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
34 | Praveen Tiwari, Raj S. Mitra |
Hybrid Verification of Protocol Bridges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(2), pp. 124-131, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
serial protocol, hybrid verification, protocol bridge, model checking, formal verification |
34 | Enrico Tronci, Giuseppe Della Penna, Benedetto Intrigila, Marisa Venturini Zilli |
A Probabilistic Approach to Automatic Verification of Concurrent Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSEC ![In: 8th Asia-Pacific Software Engineering Conference (APSEC 2001), 4-7 December 2001, Macau, China, pp. 317-324, 2001, IEEE Computer Society, 0-7695-1408-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Automatic Verification and Validation, Distributed Systems, Model Checking, Embedded Systems, Formal Methods, Reactive Systems, Concurrent Systems, Probabilistic Verification |
34 | George W. Ernst, Raymond J. Hookway, William F. Ogden |
Modular Verification of Data Abstractions with Shared Realizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 20(4), pp. 288-307, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
shared realizations, realization level data structure, abstract specification, data structures, semantics, program verification, specification languages, data abstractions, quantification, modular verification, modular specification |
34 | Yoav Hollander |
Is Verification Getting Too Complex? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 4, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Itai Yarom, Viji Patil |
Smart-Lint: Improving the Verification Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software, Verification and Testing, Second International Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, 2006. Revised Selected Papers, pp. 81-91, 2006, Springer, 978-3-540-70888-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Moab Arar, Michael L. Behm, Odellia Boni, Raviv Gal, Alex Goldin, Maxim Ilyaev, Einat Kermany, John R. Reysa, Bilal Saleh, Klaus-Dieter Schubert, Gil Shurek, Avi Ziv |
The Verification Cockpit - Creating the Dream Playground for Data Analytics over the Verification Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 11th International Haifa Verification Conference, HVC 2015, Haifa, Israel, November 17-19, 2015, Proceedings, pp. 51-66, 2015, Springer, 978-3-319-26286-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
34 | Nicolas Halbwachs, Fabienne Lagnier, Christophe Ratel |
Programming and Verifying Real-Time Systems by Means of the Synchronous Data-Flow Language LUSTRE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 18(9), pp. 785-793, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
data-flow language LUSTRE, synchronous data-flow language, critical real-time systems, ergonomy, dataflow approach, traditional description tools, verification tool LESAR, critical properties, real-time systems, parallel programming, program verification, program verification, parallel languages, verification methods, formal design |
34 | Luan Ling Lee, Toby Berger, Erez Aviczer |
Reliable On-Line Human Signature Verification Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 18(6), pp. 643-647, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
human signature verification, point-of-sale, point-of-delivery, Signature verification, forgery, on-line signature verification, dynamic signature verification |
33 | Fuchun Guo, Yi Mu 0001, Zhide Chen |
Efficient Batch Verification of Short Signatures for a Single-Signer Setting without Random Oracles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSEC ![In: Advances in Information and Computer Security, Third International Workshop on Security, IWSEC 2008, Kagawa, Japan, November 25-27, 2008. Proceedings, pp. 49-63, 2008, Springer, 978-3-540-89597-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
short signature, Batch verification |
33 | C. Richard Ho, Michael Theobald, Martin M. Deneroff, Ron O. Dror, Joseph Gagliardo, David E. Shaw |
Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 268-271, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
conditional coverage, inconclusive results, formal verification, code coverage, verifiability, coverage hole |
33 | Alon Gluska |
Coverage-oriented verification of banias. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 280-285, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
logic design, coverage, logic verification, functional coverage |
33 | Vangalur S. Alagar, D. Muthiayen |
Towards a mechanical verification of real-time reactive systems modeled in UML. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 245-254, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Prototype Verification System, real-time systems, UML, Unified Modeling Language, formal specification, object-oriented programming, program verification, specification languages, PVS, notation, safety-critical applications, mechanical verification, real-time reactive systems, design analysis, object-based systems |
33 | Florian Krohm, Andreas Kuehlmann, Arjen Mets |
The use of random simulation in formal verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 371-376, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
random simulation, BDD-based verification, counter example pattern, design partitioning, Boolean reasoning, formal verification, formal verification, hardware designs, functional equivalence |
33 | Xu-Hong Xiao, Ru-Wei Dai |
A hierarchical on-line Chinese signature verification system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: Third International Conference on Document Analysis and Recognition, ICDAR 1995, August 14 - 15, 1995, Montreal, Canada. Volume I, pp. 202-205, 1995, IEEE Computer Society, 0-8186-7128-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Chinese signature verification, static features, statistic decision, input primitive string, reference primitive string, attributed automaton, reference databases, feature extraction, feature extraction, handwriting recognition, template matching, on-line, signature verification, verification processes, dynamic features |
32 | Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi |
Synthesizing "Verification Aware" Models: Why and How? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 50-56, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Rajesh K. Gupta 0001, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi |
Formal verification - prove it or pitch it. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 710-711, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Jainendra Kumar, Carl Pixley |
Logic and Functional Verification in a Commercial Semiconductor Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 1st International Conference on Application of Concurrency to System Design (ACSD '98), 23-26 March 1998, Fukushima, Japan, pp. 8-15, 1998, IEEE Computer Society, 0-8186-8350-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Tun Li, Sikun Li, Jinshan Yu, Yang Guo 0003 |
A Novel Collaborative Verification Environment for SoC Co-Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCWD ![In: Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, CSCWD 2007, April 26-28, 2007, Melbourne, Australia, pp. 145-150, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Noah Bamford, Rekha Bangalore, Eric Chapman, Hector Chavez, Rajeev Dasari, Yinfang Lin, Edgar Jimenez |
Challenges in System on Chip Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA, pp. 52-60, 2006, IEEE Computer Society, 978-0-7695-2839-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Neha Rungta, Eric G. Mercer |
A Meta Heuristic for Effectively Detecting Concurrency Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 23-37, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Dorit Baras, Laurent Fournier, Avi Ziv |
Automatic Boosting of Cross-Product Coverage Using Bayesian Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 53-67, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Brian Bailey |
Can Mutation Analysis Help Fix Our Broken Coverage Metrics?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 5, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Frederic Doucet, R. K. Shyamasundar, Ingolf H. Krüger, Saurabh Joshi 0001, Rajesh K. Gupta 0001 |
Reactivity in SystemC Transaction-Level Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 34-50, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Ales Smrcka, Tomás Vojnar |
Verifying Parametrised Hardware Designs Via Counter Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 51-68, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Jonathan S. Ostroff |
Automated Verification of Timed Transition Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Automatic Verification Methods for Finite State Systems ![In: Automatic Verification Methods for Finite State Systems, International Workshop, Grenoble, France, June 12-14, 1989, Proceedings, pp. 247-256, 1989, Springer, 3-540-52148-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
32 | Jørgen Staunstrup, Stephen J. Garland, John V. Guttag |
Localized Verification of Circuit Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Automatic Verification Methods for Finite State Systems ![In: Automatic Verification Methods for Finite State Systems, International Workshop, Grenoble, France, June 12-14, 1989, Proceedings, pp. 349-364, 1989, Springer, 3-540-52148-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
32 | Rajeev K. Ranjan 0001, Claudionor Coelho, Sebastian Skalberg |
Beyond verification: leveraging formal for debugging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 648-651, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
behavioral indexing, post-silicon debugging, traceless debugging, formal verification, debugging, property verification |
32 | Philip W. L. Fong |
Pluggable verification modules: an extensible protection mechanism for the JVM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA ![In: Proceedings of the 19th Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2004, October 24-28, 2004, Vancouver, BC, Canada, pp. 404-418, 2004, ACM, 1-58113-831-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Aegis VM, extensible protection mechanism, pluggable verification modules, proof linking, Java virtual machine, bytecode verification, extensible systems, mobile code security |
32 | Farn Wang, Pao-Ann Hsiung |
Efficient and User-Friendly Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(1), pp. 61-83, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
software engineering, real-time systems, model-checking, Verification, formal methods, timed automata, compositional verification |
32 | Edgard Nyssen, Hichem Sahli, Kui Zhang |
A Multi-stage Online Signature Verification System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Pattern Anal. Appl. ![In: Pattern Anal. Appl. 5(3), pp. 288-295, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Function-based method, Handwritten text processing, Multi-stage verification, Parameter-based method, Pattern matching Signature verification |
32 | Brigitte Wirtz |
Stroke-based time warping for signature verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: Third International Conference on Document Analysis and Recognition, ICDAR 1995, August 14 - 15, 1995, Montreal, Canada. Volume I, pp. 179-182, 1995, IEEE Computer Society, 0-8186-7128-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
stroke-based time warping, function-based signature verification, positional data, 3D nonlinear correlation, signature signals, stroke index, DP index, finite state automaton, reference strokes, dynamic programming, dynamic programming, handwriting recognition, image matching, finite automata, authorisation, correlation methods, pressure, dynamic data, dynamic signature verification |
31 | Robert P. Kurshan |
Scaling Commercial Verification to Larger Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 8-13, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Mark A. Hillebrand, Wolfgang J. Paul |
On the Architecture of System Verification Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 153-168, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Tobias Schüle, Klaus Schneider 0001 |
Verification of Data Paths Using Unbounded Integers: Automata Strike Back. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software, Verification and Testing, Second International Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, 2006. Revised Selected Papers, pp. 65-80, 2006, Springer, 978-3-540-70888-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong |
Guess, solder, measure, repeat: how do I get my mixed-signal chip right? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 520-521, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Verilog-AMS, analog behavioral modeling, low power verification, mixed-signal verification, VHDL, SPICE, functional verification, Verilog, performance verification |
31 | Aythami Morales, Miguel Angel Ferrer-Ballester, Marcos Faúndez-Zanuy, Joan Fabregas, Guillermo González de Rivera, Javier Garrido Salas, Ricardo Ribalda, Javier Ortega, Manuel R. Freire |
Biometric System Verification Close to "Real World" Conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COST 2101/2102 Conference ![In: Biometric ID Management and Multimodal Communication, Joint COST 2101 and 2102 International Conference, BioID_MultiComm 2009, Madrid, Spain, September 16-18, 2009. Proceedings, pp. 236-243, 2009, Springer, 978-3-642-04390-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
hand-geometry verification, contact-less, online signature verification, speech verification, Biometric, face verification |
31 | Pei-Hsin Ho, Adrian J. Isles, Timothy Kam |
Formal verification of pipeline control using controlled token nets and abstract interpretation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998, pp. 529-536, 1998, ACM / IEEE Computer Society, 1-58113-008-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
controlled token net, pipeline control verification, model checking, formal verification, computer-aided design, abstract interpretation, functional verification, processor verification |
31 | Rajdeep Mukhopadhyay, Subrat Kumar Panda, Pallab Dasgupta, John Gough |
Instrumenting AMS assertion verification on commercial platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(2), pp. 21:1-21:47, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
OVL, SVA, integrated mixed signal design, verification library, simulation, Assertion |
31 | Karen Zee, Viktor Kuncak, Martin C. Rinard |
Full functional verification of linked data structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2008 Conference on Programming Language Design and Implementation, Tucson, AZ, USA, June 7-13, 2008, pp. 349-361, 2008, ACM, 978-1-59593-860-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
java, verification, data structure, decision procedure, theorem prover |
31 | Xi Chen 0024, Harry Hsieh, Felice Balarin |
Verification Approach of Metropolis Design Framework for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 34(1), pp. 3-27, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
metropolis, simulation, formal verification, meta-model, spin, LTL, property, LOC |
31 | June Andronick, Boutheina Chetali, Christine Paulin-Mohring |
Formal Verification of Security Properties of Smart Card Embedded Source Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FM ![In: FM 2005: Formal Methods, International Symposium of Formal Methods Europe, Newcastle, UK, July 18-22, 2005, Proceedings, pp. 302-317, 2005, Springer, 3-540-27882-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Source code verification, Security, Formal Methods, Theorem Proving, Smart Card |
31 | Chuchang Liu, Maris A. Ozols, Marie Henderson, Anthony Cant |
Towards Certificate Verification in a Certificate Management System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSC ![In: 23rd Australasian Computer Science Conference (ACSC 2000), 31 January - 3 February 2000, Canberra, Australia, pp. 150-157, 2000, IEEE Computer Society, 0-7695-0518-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
CA (Certificate Authority), certificate management systems, certificate verification, formal methods, information security, certificate |
31 | Anil K. Jain 0001, Lin Hong, Ruud M. Bolle |
On-Line Fingerprint Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 19(4), pp. 302-314, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
ridge extraction, verification, Biometrics, matching, fingerprints, minutia, orientation field |
30 | Giuseppe Della Penna, Benedetto Intrigila, Enrico Tronci, Marisa Venturini Zilli |
Exploiting Transition Locality in the Disk Based Mur phi Verifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings, pp. 202-219, 2002, Springer, 3-540-00116-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Shmuel Ur, Elad Yom-Tov, Paul Wernick |
An Open Source Simulation Model of Software Development and Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software, Verification and Testing, Second International Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, 2006. Revised Selected Papers, pp. 124-137, 2006, Springer, 978-3-540-70888-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Simulation, Performance, Design, Algorithms, Reliability, Verification, Measurement, Software Development, Management, Theory, Experimentation, Economics, Iterative design |
30 | Alicia Strang, David Potts, Shankar Hemmady |
A Holistic Approach to SoC Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 417-422, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
holistic verification, verification management, right-brained thinking, verification, debug, SoC, visualization environments |
30 | Íñigo Ugarte, Pablo Sanchez |
Verification of Embedded Systems Based on Interval Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 33(6), pp. 697-720, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Embedded system verification, design for verification, interval analysis, assertion-based verification |
30 | I. S. W. B. Prasetya, A. Azurat, Tanja E. J. Vos, Arthur van Leeuwen |
Building Verification Condition Generators by Compositional Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEFM ![In: Third IEEE International Conference on Software Engineering and Formal Methods (SEFM 2005), 7-9 September 2005, Koblenz, Germany, pp. 220-230, 2005, IEEE Computer Society, 0-7695-2435-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
modular verification, verification tool, verification technique |
30 | Issa Traoré, Demissie B. Aredo |
Enhancing Structured Review with Model-Based Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 30(11), pp. 736-753, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Structured review, prototype verification system (PVS), model-based verification, UML, formal methods, OCL, validation and verification |
30 | Flor Ramírez Rioja, Mariko Nakano-Miyatake, Héctor M. Pérez Meana, Karina Toscano |
Dynamics features Extraction for on-Line Signature verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONIELECOMP ![In: 14th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2004), 16-18 February 2004, Veracruz, Mexico, pp. 156-161, 2004, IEEE Computer Society, 0-7695-2074-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
extraction of dynamics characteristics, forgery detection and off-line signature verification, Signature verification, dynamics verification |
30 | Dariusz Z. Lejtman, Susan E. George |
On-line Handwritten Signature Verification Using Wavelets and Back-propagation Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: 6th International Conference on Document Analysis and Recognition (ICDAR 2001), 10-13 September 2001, Seattle, WA, USA, pp. 992-996, 2001, IEEE Computer Society, 0-7695-1263-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Handwritten signature verification, Neural networks, Pattern recognition, Wavelet transform, On-line signature verification, Dynamic signature verification |
30 | Hans Samsom, Frank H. M. Franssen, Francky Catthoor, Hugo De Man |
System level verification of video and image processing specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 144-149, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
formal verification method, front-end telecom, image processing specifications, loop ordering, system level verification, computational complexity, image processing, complexity, formal specification, formal verification, video processing, numerical computing |
30 | Bernard Berthomieu, Michel Diaz |
Modeling and Verification of Time Dependent Systems Using Time Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 17(3), pp. 259-273, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
time dependent systems, explicit values, time-dependent systems, verification, formal specification, parallel programming, Petri nets, protocols, formal verification, specification, program verification, time Petri nets, concurrent systems, communication systems, alternating bit protocol |
30 | Aysu Betin-Can, Tevfik Bultan |
Highly dependable concurrent programming using design for verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Aspects Comput. ![In: Formal Aspects Comput. 19(2), pp. 243-268, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Model checking, Synchronization, Design patterns, Interfaces, Concurrent programming |
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