Search results for "Xeon®"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
101	Subhash Saini, Andrey Naraikin, Rupak Biswas, David Barkai, Timothy Sandstrom	Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications.	SC	2009	DBLP DOI BibTeX RDF
80	Pawel Gepner, David L. Fraser, Michal Filip Kowalik	Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications.	ICCS (1)	2008	DBLP DOI BibTeX RDF	quad-core processors, parallel processing, benchmarks, HPC, multi-core processors
73	Raj Varada, Mysore Sriram, Kris Chou, James Guzzo	Design and integration methods for a multi-threaded dual core 65nm Xeon® processor.	ICCAD	2006	DBLP DOI BibTeX RDF	Xeon®, Integration, Design Methods, processor
43	John C. Linford, Adrian Sandu	Optimizing large scale chemical transport models for multicore platforms.	SpringSim	2008	DBLP DOI BibTeX RDF	IBM cell broadband engine, Intel quad-core xeon, time splitting, scalability, multicore, domain decomposition, chemical transport model
42	Pawel Gepner, David L. Fraser, Michal Filip Kowalik	Performance Evolution and Power Benefits of Cluster System Utilizing Quad-Core and Dual-Core Intel Xeon Processors.	PPAM	2007	DBLP DOI BibTeX RDF	dual-core processors, quad-core processors, parallel processing, benchmarks, HPC, multi-core processors
42	Ramesh Radhakrishnan, Rizwan Ali, Garima Kochhar, Kalyana Chadalavada, Ramesh Rajagopalan, Jenwei Hsieh, Onur Celebioglu	Evaluating Performance of BLAST on Intel Xeon and Itanium2 Processors.	ISPA	2004	DBLP DOI BibTeX RDF
38	Daisuke Takahashi	An Implementation of Parallel 1-D FFT Using SSE3 Instructions on Dual-Core Processors.	PARA	2006	DBLP DOI BibTeX RDF
34	Galen M. Shipman, Sriram Swaminarayan, Gary Grider, Jim Lujan, R. Joseph Zerr	Early Performance Results on 4th Gen Intel(R) Xeon (R) Scalable Processors with DDR and Intel(R) Xeon(R) processors, codenamed Sapphire Rapids with HBM.	CoRR	2022	DBLP DOI BibTeX RDF
34	Xing Guo, Zhensen Wu, Jiaji Wu, Yunhua Cao	Parallel BRDF-based infrared radiation simulation of aerial targets implemented on Intel Xeon processor and Xeon Phi coprocessor.	J. Real Time Image Process.	2019	DBLP DOI BibTeX RDF
34	Tetyana Gerasimova, Alla Nesterenko	Паралельні алгоритми розв'язування систем нелінійних рівнянь та задач Коші для систем звичайних диференціальних рівнянь на багатоядерних комп'ютерах з процесорами Intel Xeon Phi Parallel algorithms for the solving both of non-linear systems and initial-value problems for systems of ordinary differential equations on multi-core computers with processors Intel Xeon Phi.	UkrPROG	2018	DBLP BibTeX RDF
34	Thiago Teixeira, Frederico Luís Cabral, Carla Osthoff, Marcio Rentes Borges, Roberto Pinto Souto	Analysis of Optimization Opportunities for Intel Xeon Phi and Intel Xeon Scalable Processors Environments of a Numerical Method for the Biphasic Flow of Fluids in Porous Media.	WSCAD	2018	DBLP DOI BibTeX RDF
34	Pawel Czarnul	Benchmarking Parallel Chess Search in Stockfish on Intel Xeon and Intel Xeon Phi Processors.	ICCS (3)	2018	DBLP DOI BibTeX RDF
34	Chun-Yuan Lin, Huang Ting Yen, Che-Lun Hung	Compressing three-dimensional sparse arrays using inter- and intra-task parallelization strategies on Intel Xeon and Xeon Phi.	J. Supercomput.	2017	DBLP DOI BibTeX RDF
34	Pawel Czarnul	Benchmarking Performance of a Hybrid Intel Xeon/Xeon Phi System for Parallel Computation of Similarity Measures Between Large Vectors.	Int. J. Parallel Program.	2017	DBLP DOI BibTeX RDF
34	George Chatzikonstantis, Dimitrios Rodopoulos, Christos Strydis, Chris I. De Zeeuw, Dimitrios Soudris	Optimizing Extended Hodgkin-Huxley Neuron Model Simulations for a Xeon/Xeon Phi Node.	IEEE Trans. Parallel Distributed Syst.	2017	DBLP DOI BibTeX RDF
34	George Chatzikonstantis, Dimitrios Rodopoulos, Sofia Nomikou, Christos Strydis, Chris I. De Zeeuw, Dimitrios Soudris	First impressions from detailed brain model simulations on a Xeon/Xeon-Phi node.	Conf. Computing Frontiers	2016	DBLP DOI BibTeX RDF
34	Jirí Hanzelka, Robert Skopal, Katerina Slaninová, Jan Martinovic, Jiri Dvorský	Graph Problems Performance Comparison Using Intel Xeon and Intel Xeon-Phi.	ACSS (1)	2016	DBLP DOI BibTeX RDF
34	Dheemanth Nagaraj, Chris Gianos	Intel® Xeon® Processor D: The First Xeon processor optimized for dense solutions.	Hot Chips Symposium	2015	DBLP DOI BibTeX RDF
34	Nishant Agrawal, Paul Edwards, Ambuj Pandey, Michael Klemm, Ravi Ojha, Rihab Abdul Razak	Performance Evaluation of OpenFOAM* with MPI-3 RMA Routines on Intel® Xeon® Processors and Intel® Xeon Phi™ Coprocessors.	EuroMPI	2015	DBLP DOI BibTeX RDF
34	Chun-Yuan Lin, Huang Ting Yen, Che-Lun Hung	Efficient Strategies of Compressing Three-Dimensional Sparse Arrays Based on Intel XEON and Intel XEON Phi Environments.	CIT/IUCC/DASC/PICom	2015	DBLP DOI BibTeX RDF
34	Benny Mathew, Nitin Rai, Apaar Gupta, Amit Harode	Exploiting computing power of Xeon and Intel Xeon Phi for a molecular dynamics application.	SpringSim (HPS)	2015	DBLP BibTeX RDF
34	Adrian Jackson, Mateusz Iwo Dubaniowski	LU Factorisation on Xeon and Xeon Phi Processors.	PARCO	2015	DBLP DOI BibTeX RDF
34	Lars Koesterke, James E. Koltes, Nathan T. Weeks, Kent F. Milfeld, Matthew W. Vaughn, James M. Reecy, Daniel Stanzione	Discovery of biological networks using an optimized partial correlation coefficient with information theory algorithm on Stampede's Xeon and Xeon Phi processors.	Concurr. Comput. Pract. Exp.	2014	DBLP DOI BibTeX RDF
34	Simon J. Pennycook, Christopher J. Hughes, Mikhail Smelyanskiy, Stephen A. Jarvis	Exploring SIMD for Molecular Dynamics, Using Intel® Xeon® Processors and Intel® Xeon Phi Coprocessors.	IPDPS	2013	DBLP DOI BibTeX RDF
34	Lars Koesterke, Kent F. Milfeld, Matthew W. Vaughn, Daniel Stanzione, James E. Koltes, Nathan T. Weeks, James M. Reecy	Optimizing the PCIT algorithm on stampede's Xeon and Xeon Phi processors for faster discovery of biological networks.	XSEDE	2013	DBLP DOI BibTeX RDF
31	Craig P. Steffen, Gildas Genest	Nallatech In-Socket FPGA Front-Side Bus Accelerator.	Comput. Sci. Eng.	2010	DBLP DOI BibTeX RDF	Xeon, Field-programmable gate arrays, compiler, reconfigurable, bandwidth, accelerators, Xilinx
30	Ryan E. Grant, Ahmad Afsahi	A Comprehensive Analysis of OpenMP Applications on Dual-Core Intel Xeon SMPs.	IPDPS	2007	DBLP DOI BibTeX RDF
30	Terry Moreland, Chih Jeng Kenneth Tan	Performance of Linear Algebra Code: Intel Xeon EM64T and ItaniumII Case Examples.	ICCSA (4)	2005	DBLP DOI BibTeX RDF	Systems of linear algebraic equations, Architecture specific tuning, Eigensolvers, SVD, Eigenvalues, Linear solver, Diagonalizer
30	Greg J. Regnier, Dave B. Minturn, Gary L. McAlpine, Vikram A. Saletore, Annie P. Foong	ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine.	IEEE Micro	2004	DBLP DOI BibTeX RDF
25	Jorge Guerra, Wendy Belluomini, Joseph S. Glider, Karan Gupta, Himabindu Pucha	Energy proportionality for storage: impact and feasibility.	ACM SIGOPS Oper. Syst. Rev.	2010	DBLP DOI BibTeX RDF
25	John Robert Wernsing, Greg Stitt	Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing.	LCTES	2010	DBLP DOI BibTeX RDF	elastic computing, fpga, multi-core, speedup, heterogeneous architectures
25	Yasuko Watanabe, John D. Davis, David A. Wood 0001	WiDGET: Wisconsin decoupled grid execution tiles.	ISCA	2010	DBLP DOI BibTeX RDF	instruction steering, power proportional computing, performance, hardware, power efficiency
25	Richard W. Linderman	GPGPU role within a 500 TFLOPS heterogeneous cluster.	GPGPU	2010	DBLP DOI BibTeX RDF
25	Surendra Byna, Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Srihari Cadambi	Best-effort semantic document search on GPUs.	GPGPU	2010	DBLP DOI BibTeX RDF	best-effort computing, dependency relaxation, supervised semantic indexing, GPGPU, CUDA, document search
25	John C. Linford, Adrian Sandu	Vector stream processing for effective application of heterogeneous parallelism.	SAC	2009	DBLP DOI BibTeX RDF	dimension splitting, vector stream processing, modeling, cell broadband engine, chemical transport modeling
25	Pavan Yalamanchili, Sumod K. Mohan, Tarek M. Taha	Implementing a hierarchical Bayesian visual cortex model on multi-core processors.	ACM Southeast Regional Conference	2009	DBLP DOI BibTeX RDF	performance, measurement, experimentation
25	Jun Shirako, David M. Peixotto, Vivek Sarkar, William N. Scherer III	Phaser accumulators: A new reduction construct for dynamic parallelism.	IPDPS	2009	DBLP DOI BibTeX RDF
25	Georgios Tournavitis, Zheng Wang 0001, Björn Franke, Michael F. P. O'Boyle	Towards a holistic approach to auto-parallelization: integrating profile-driven parallelism detection and machine-learning based mapping.	PLDI	2009	DBLP DOI BibTeX RDF	auto-parallelization, machine-learning based parallelism mapping, profile-driven parallelism detection, openmp
25	Fabrizio Petrini, Virat Agarwal, Davide Pasetto	SCAMPI: a scalable CAM-based algorithm for multiple pattern inspection.	SC	2009	DBLP DOI BibTeX RDF
25	John C. Linford, John Michalakes, Manish Vachharajani, Adrian Sandu	Multi-core acceleration of chemical kinetics for simulation and prediction.	SC	2009	DBLP DOI BibTeX RDF	chemical kinetics, kinetic preprocessor, open-MP, multi-core, cell broadband engine, NVIDIA CUDA, atmospheric modeling
25	David M. Kunzman, Laxmikant V. Kalé	Towards a framework for abstracting accelerators in parallel applications: experience with cell.	SC	2009	DBLP DOI BibTeX RDF
25	Erik A. Hendriks, Ronald G. Minnich	How to build a fast and reliable 1024 node cluster with only one disk.	J. Supercomput.	2006	DBLP DOI BibTeX RDF
25	Shih-Wei Liao, Zhaohui Du, Gansha Wu, Guei-Yuan Lueh	Data and Computation Transformations for Brook Streaming Applications on Multiprocessors.	CGO	2006	DBLP DOI BibTeX RDF
25	Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, Hiroshi Nakashima, Hiroshi Nakamura, Satoshi Matsuoka, Yoshihiko Hotta	MegaProto/E: power-aware high-performance cluster with commodity technology.	IPDPS	2006	DBLP DOI BibTeX RDF
25	Yaoping Ruan, Vivek S. Pai, Erich M. Nahum, John M. Tracey	Evaluating the impact of simultaneous multithreading on network servers using real hardware.	SIGMETRICS	2005	DBLP DOI BibTeX RDF	simultaneous multithreading(SMT), network server
25	Daisuke Takahashi, Taisuke Boku, Mitsuhisa Sato	An Implementation of Parallel 3-D FFT Using Short Vector SIMD Instructions on Clusters of PCs.	PARA	2004	DBLP DOI BibTeX RDF
25	Justin J. Song, Eric Q. Li, Wei Hu 0002, Steven Ge, Chunrong Lai, Yimin Zhang 0002, Xuegong Zhang, Wenguang Chen, Weimin Zheng	Parallelization of Bayesian Network based SNPs Pattern Analysis and Performance Characterization on SMP/HT.	ICPADS	2004	DBLP DOI BibTeX RDF
25	Matthias Kühnemann, Thomas Rauber, Gudula Rünger	Improving the execution time of global communication operations.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	global communication operations, orthogonal processor groups, parallel programs, MPI
17	Keiichiro Fukazawa, Riki Takahashi	Performance Evaluation of the Fourth-Generation Xeon with Different Memory Characteristics.	HPC Asia Workshops	2024	DBLP DOI BibTeX RDF
17	Ashley O. Munch, Nevine Nassif, Carleton L. Molnar, Jason Crop, Rich Gammack, Chinmay P. Joshi, Goran Zelic, Kambiz Munshi, Min Huang, Charles Morganti, Sireesha Kandula, Arijit Biswas	2.3 Emerald Rapids: 5th-Generation Intel® Xeon® Scalable Processors.	ISSCC	2024	DBLP DOI BibTeX RDF
17	Reese Kuper, Ipoom Jeong, Yifan Yuan, Ren Wang 0001, Narayan Ranganathan, Nikhil Rao, Jiayu Hu, Sanjay Kumar, Philip Lantz, Nam Sung Kim	A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors.	ASPLOS (2)	2024	DBLP DOI BibTeX RDF
17	Lakshmi Arunachalam, Fahim Mohammad, Vrushabh H. Sanghavi	Distributed Transfer Learning with 4th Gen Intel Xeon Processors.	CoRR	2023	DBLP DOI BibTeX RDF
17	István Z. Reguly	Comparative evaluation of bandwidth-bound applications on the Intel Xeon CPU MAX Series.	CoRR	2023	DBLP DOI BibTeX RDF
17	Reese Kuper, Ipoom Jeong, Yifan Yuan, Jiayu Hu, Ren Wang 0001, Narayan Ranganathan, Nam Sung Kim	A Quantitative Analysis and Guideline of Data Streaming Accelerator in Intel 4th Gen Xeon Scalable Processors.	CoRR	2023	DBLP DOI BibTeX RDF
17	Yoosang Park, Raehyun Kim, Thi My Tuyen Nguyen, Jaeyoung Choi	Improving blocked matrix-matrix multiplication routine by utilizing AVX-512 instructions on intel knights landing and xeon scalable processors.	Clust. Comput.	2023	DBLP DOI BibTeX RDF
17	Don Soltis, Stephen Robinson	The Next Generation of High Performance, Energy-Efficient Computing: Intel® Xeon® Processors Built on Efficient-Core.	HCS	2023	DBLP DOI BibTeX RDF
17	Chris Gianos	Architecting for Flexibility and Value with Next Gen Intel® Xeon® Processors.	HCS	2023	DBLP DOI BibTeX RDF
17	Ivan Lirkov, Marcin Paprzycki, Maria Ganzha	Performance Analysis of a 3D Elliptic Solver on Intel Xeon Computer System.	FedCSIS	2023	DBLP DOI BibTeX RDF
17	John D. McCalpin	Bandwidth Limits in the Intel Xeon Max (Sapphire Rapids with HBM) Processors.	ISC Workshops	2023	DBLP DOI BibTeX RDF
17	George Katevenis, Manolis Ploumidis, Manolis Marazakis	Impact of Cache Coherence on the Performance of Shared-Memory based MPI Primitives: A Case Study for Broadcast on Intel Xeon Scalable Processors.	ICPP	2023	DBLP DOI BibTeX RDF
17	István Z. Reguly	Comparative evaluation of bandwidth-bound applications on the Intel Xeon CPU MAX Series.	SC Workshops	2023	DBLP DOI BibTeX RDF
17	Shinobu Miwa, Shin'ichiro Matsuo	Analyzing the Performance Impact of HPC Workloads with Gramine+SGX on 3rd Generation Xeon Scalable Processors.	SC Workshops	2023	DBLP DOI BibTeX RDF
17	Meena Arunachalam, Vrushabh Sanghavi, Yi A. Yao, Yi A Zhou, Lifeng A. Wang, Zongru Wen, Niroop Ammbashankar, Ning W. Wang, Fahim Mohammad	Strategies for Optimizing End-to-End Artificial Intelligence Pipelines on Intel Xeon Processors.	CoRR	2022	DBLP DOI BibTeX RDF
17	Praveen Mosur	Built for the Edge: The Next-Generation Intel® Xeon D 2700 & 1700 processors.	HCS	2022	DBLP DOI BibTeX RDF
17	Hyungmin Cho	Know Your Neighbor: Physically Locating Xeon Processor Cores on the Core Tile Grid.	DATE	2022	DBLP DOI BibTeX RDF
17	Nevine Nassif, Ashley O. Munch, Carleton L. Molnar, Gerald Pasdast, Sitaraman V. Lyer, Zibing Yang, Oscar Mendoza, Mark Huddart, Srikrishnan Venkataraman, Sireesha Kandula, Rafi Marom, Alexandra M. Kern, William J. Bowhill, David R. Mulvihill, Srikanth Nimmagadda, Varma Kalidindi, Jonathan Krause, Mohammad M. Haq, Roopali Sharma, Kevin Duda	Sapphire Rapids: The Next-Generation Intel Xeon Scalable Processor.	ISSCC	2022	DBLP DOI BibTeX RDF
17	Fang Huang 0001, Hao Yang 0020, Jian Tao, Jian Wang 0079, Xicheng Tan	Preliminary study on the automatic parallelism optimization model for image enhancement algorithms based on Intel's® Xeon Phi.	Concurr. Comput. Pract. Exp.	2021	DBLP DOI BibTeX RDF
17	Ji Hoon Kang 0002, Jinyul Hwang, Hyung Jin Sung, Hoon Ryu	High-performance simulations of turbulent boundary layer flow using Intel Xeon Phi many-core processors.	J. Supercomput.	2021	DBLP DOI BibTeX RDF
17	Chao-Tung Yang, Jung-Chun Liu, Yu-Wei Chan, Endah Kristiani, Chan-Fu Kuo	Performance benchmarking of deep learning framework on Intel Xeon Phi.	J. Supercomput.	2021	DBLP DOI BibTeX RDF
17	Jesmin Jahan Tithi, Fabio Checconi, Douglas Doerfler, Fabrizio Petrini	Performance Optimization of SU3_Bench on Xeon and Programmable Integrated Unified Memory Architecture.	CoRR	2021	DBLP BibTeX RDF
17	Jesmin Jahan Tithi, Fabrizio Petrini	A New Parallel Algorithm for Sinkhorn Word-Movers Distance and Its Performance on PIUMA and Xeon CPU.	CoRR	2021	DBLP BibTeX RDF
17	Manuel Costanzo, Enzo Rucci, Ulises Costi, Franco Chichizola, Marcelo R. Naiouf	Comparison of HPC Architectures for Computing All-Pairs Shortest Paths. Intel Xeon Phi KNL vs NVIDIA Pascal.	CoRR	2021	DBLP BibTeX RDF
17	Sparsh Mittal	A survey on evaluating and optimizing performance of Intel Xeon Phi.	Concurr. Comput. Pract. Exp.	2020	DBLP DOI BibTeX RDF
17	Andrés Rodríguez 0001, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran, Darío Suárez Gracia, José L. Núñez-Yáñez	Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform.	J. Supercomput.	2020	DBLP DOI BibTeX RDF
17	Gary Lawson, Masha Sosonkina, Tal Ezer, Yuzhong Shen	Applying EMD/HHT analysis to power traces of applications executed on systems with Intel Xeon Phi.	Int. J. High Perform. Comput. Appl.	2020	DBLP DOI BibTeX RDF
17	Mario Hernández, Juan M. Cebrian, José M. Cecilia, José M. García 0001	Offloading strategies for Stencil kernels on the KNC Xeon Phi architecture: Accuracy versus performance.	Int. J. High Perform. Comput. Appl.	2020	DBLP DOI BibTeX RDF
17	Lukasz Szustak, Roman Wyrzykowski, Tomasz Olas, Valeria Mele	Correlation of Performance Optimizations and Energy Consumption for Stencil-Based Application on Intel Xeon Scalable Processors.	IEEE Trans. Parallel Distributed Syst.	2020	DBLP DOI BibTeX RDF
17	Mireya Paredes, Graham D. Riley, Mikel Luján	Exploiting Parallelism and Vectorisation in Breadth-First Search for the Intel Xeon Phi.	IEEE Trans. Parallel Distributed Syst.	2020	DBLP DOI BibTeX RDF
17	Guohua You, Xuejing Wang	A server-side accelerator framework for multi-core CPUs and Intel Xeon Phi co-processor systems.	Clust. Comput.	2020	DBLP DOI BibTeX RDF
17	Irma Esmer Papazian	New 3rd Gen Intel® Xeon® Scalable Processor (Codename: Ice Lake-SP).	Hot Chips Symposium	2020	DBLP DOI BibTeX RDF
17	Thi My Tuyen Nguyen, Yoosang Park, Jaeyoung Choi, Raehyun Kim	Evaluating performance of Parallel Matrix Multiplication Routine on Intel KNL and Xeon Scalable Processors.	ACSOS Companion	2020	DBLP DOI BibTeX RDF
17	Thomas Charest, Robert C. Green II	Implementing Central Force optimization on the Intel Xeon Phi.	IPDPS Workshops	2020	DBLP DOI BibTeX RDF
17	Hancheng Wu, Michela Becchi	Evaluating Thread Coarsening and Low-cost Synchronization on Intel Xeon Phi.	IPDPS	2020	DBLP DOI BibTeX RDF
17	Manuel Costanzo, Enzo Rucci, Ulises Costi, Franco Chichizola, Marcelo R. Naiouf	Comparison of HPC Architectures for Computing All-Pairs Shortest Paths. Intel Xeon Phi KNL vs NVIDIA Pascal.	CACIC	2020	DBLP DOI BibTeX RDF
17	Haoran Zhao, Tian Xia 0008, Chenyang Li, Wenzhe Zhao, Nanning Zheng 0001, Pengju Ren	Exploring Better Speculation and Data Locality in Sparse Matrix-Vector Multiplication on Intel Xeon.	ICCD	2020	DBLP DOI BibTeX RDF
17	Victoria Sanz, Adrián Pousa, Marcelo R. Naiouf, Armando De Giusti	Accelerating Pattern Matching on Intel Xeon Phi Processors.	ICA3PP (1)	2020	DBLP DOI BibTeX RDF
17	Fredrik Robertsen, Keijo Mattila, Jan Westerholm	High-performance SIMD implementation of the lattice-Boltzmann method on the Xeon Phi processor.	Concurr. Comput. Pract. Exp.	2019	DBLP DOI BibTeX RDF
17	Edoardo Coronado-Barrientos, Guillermo Indalecio Fernández, Antonio J. García-Loureiro	AXC: A new format to perform the SpMV oriented to Intel Xeon Phi architecture in OpenCL.	Concurr. Comput. Pract. Exp.	2019	DBLP DOI BibTeX RDF
17	Mohamed Arafa, Bahaa Fahim, Sailesh Kottapalli, Akhilesh Kumar, Lily Pao Looi, Sreenivas Mandava, Andy Rudoff, Ian M. Steiner, Bob Valentine, Geetha Vedaraman, Sujal Vora	Cascade Lake: Next Generation Intel Xeon Scalable Processor.	IEEE Micro	2019	DBLP DOI BibTeX RDF
17	Yuxuan Xing, Fang Liu 0002, Nong Xiao, Zhiguang Chen, Yutong Lu	Capability for Multi-Core and Many-Core Memory Systems: A Case-Study With Xeon Processors.	IEEE Access	2019	DBLP DOI BibTeX RDF
17	Andre Viebke, Suejb Memeti, Sabri Pllana, Ajith Abraham	CHAOS: a parallelization scheme for training convolutional neural networks on Intel Xeon Phi.	J. Supercomput.	2019	DBLP DOI BibTeX RDF
17	J. L. Campon, Luis Landesa	Fast solution of electromagnetic scattering problems using Xeon Phi coprocessors.	J. Supercomput.	2019	DBLP DOI BibTeX RDF
17	Raúl Nozal, Borja Pérez, José Luis Bosque, Ramón Beivide	Load balancing in a heterogeneous world: CPU-Xeon Phi co-execution of data-parallel kernels.	J. Supercomput.	2019	DBLP DOI BibTeX RDF
17	Ivan Fernandez, Alejandro Villegas, Eladio Gutiérrez, Oscar G. Plata	Accelerating time series motif discovery in the Intel Xeon Phi KNL processor.	J. Supercomput.	2019	DBLP DOI BibTeX RDF
17	Vladimir A. Mironov, Alexander A. Moskovsky, Michael D'Mello, Yuri Alexeev	An efficient MPI/OpenMP parallelization of the Hartree-Fock-Roothaan method for the first generation of Intel® Xeon Phi™ processor architecture.	Int. J. High Perform. Comput. Appl.	2019	DBLP DOI BibTeX RDF
17	Sebastián Rodríguez Leopold, Facundo Parodi, Sergio Nesmachnow	Parallel evolutionary approaches for game playing and verification using Intel Xeon Phi.	J. Parallel Distributed Comput.	2019	DBLP DOI BibTeX RDF
17	Andrey Polyakov 0001, Mikhail L. Zymbler	Parallel Algorithm for Time Series Discords Discovery on the Intel Xeon Phi Knights Landing Many-core Processor.	CoRR	2019	DBLP BibTeX RDF
17	Jacek Czaja, Michal Gallus, Tomasz Patejko, Jian Tang	Softmax Optimizations for Intel Xeon Processor-based Platforms.	CoRR	2019	DBLP BibTeX RDF
17	Chansup Byun, Jeremy Kepner, William Arcand, David Bestor, William Bergeron, Matthew Hubbell, Vijay Gadepally, Michael Houle 0001, Michael Jones 0001, Anne Klein, Lauren Milechin, Peter Michaleas, Julie Mullen, Andrew Prout, Antonio Rosa, Siddharth Samsi, Charles Yee, Albert Reuther	Optimizing Xeon Phi for Interactive Data Analysis.	CoRR	2019	DBLP BibTeX RDF
17	Stefanos Gerangelos, Georgios I. Goumas, Nectarios Koziris	Efficient accelerator sharing in virtualized environments: A Xeon Phi use-case.	J. Syst. Softw.	2019	DBLP DOI BibTeX RDF