Search results for "architectures"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
48	Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera	Radix-4 Vectoring Cordic Algorithm And Architectures.	ASAP	1996	DBLP DOI BibTeX RDF	radix-4 vectoring CORDIC algorithm, radix-4 vectoring CORDIC architectures, vectoring mode, microrotations, zero skipping technique, recursive architectures, matrix triangularization, rotation angle, computational complexity, complexity, parallel architectures, singular value decomposition, SVD, signal processing, digital arithmetic, digital arithmetic, matrix algebra, pipelined architectures
42	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures.	ASAP	2003	DBLP DOI BibTeX RDF
41	Richard T. Bechtold	Diagnostic Software Architectures.	ESPRIT ARES Workshop	1998	DBLP DOI BibTeX RDF	Diagnostic Software Architectures, Error Management, Software Families, Embedded Systems, Software Architectures
38	Roger Olmstead	Compilers and parallel architectures (abstract only): sequential to parallel mapping strategies.	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
38	Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger	A Synthesis System For Bus-Based Wavefront Array Architectures.	ASAP	1996	DBLP DOI BibTeX RDF	synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations
38	Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary	Compiler Algorithms for Optimizing Locality and Parallelism on Shared and Distributed Memory Machines.	IEEE PACT	1997	DBLP DOI BibTeX RDF	storage layout, SUN SPARCstation 5, IBM SP-2, SGI Challenge, Convex Exemplar, parallel architectures, parallel architectures, optimizing compilers, interprocessor communication, cache performance, distributed memory machines, shared memory machines, loop nests, data decomposition, compiler algorithms
37	Yan Liu 0001, Ian Gorton, Len Bass, Cuong Hoang, Suhail Abanmi	MEMS: A Method for Evaluating Middleware Architectures.	QoSA	2006	DBLP DOI BibTeX RDF
36	Carl Ebeling, Darren C. Cronquist, Paul Franklin	Configurable computing: the catalyst for high-performance architectures.	ASAP	1997	DBLP DOI BibTeX RDF	high-performance architectures, cost-performance, application-specific computation pipelines, static configuration, FPGAs, computational complexity, computer architectures, configurable computing, dynamic control, RaPiD, application-specific hardware
35	Flávio Oquendo	pi-ADL: an Architecture Description Language based on the higher-order typed pi-calculus for specifying dynamic and mobile software architectures.	ACM SIGSOFT Softw. Eng. Notes	2004	DBLP DOI BibTeX RDF	specification languages, Architecture Description Languages, ?-calculus, dynamic architectures, mobile architectures
34	D. K. Arvind 0001	Distributed simulation of parallel VLSI architectures.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
34	Patrice Quinton, Yves Robert	Algorithms and Parallel VLSI Architectures.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
34	Marc Moonen	Algorithms and architectures for recursive total least squares estimation.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
32	Anthony-Trung Nguyen, Maged M. Michael, Arun Sharma, Josep Torrellas	The Augmint multiprocessor simulation toolkit for Intel x86 architectures.	ICCD	1996	DBLP DOI BibTeX RDF	Augmint multiprocessor simulation toolkit, Intel x86 architectures, publicly available simulation tools, instruction mix, memory reference patterns, CISC architectures, execution driven multiprocessor simulation toolkit, m4 macro extended C, C++ applications, SPLASH-2 benchmark suites, thread based programming model, shared global address space, private stack space, simulator interface, MINT simulation toolkit, x8d based uniprocessor systems, multiprocessing systems, trace driven simulation, architecture simulators, uniprocessors
32	James D. Allen, David E. Schimmel	The impact of pipelining on SIMD architectures.	IPPS	1995	DBLP DOI BibTeX RDF	massively parallel SIMD architectures, stall penalties, reduction operations, Scheduling mechanisms, area costs, scheduling, parallel architectures, pipelining, program compilers, pipeline processing, performance improvement, SIMD architectures, instruction delivery
31	Krishna M. Kavi, Roberto Giorgi, Joseph Arul	Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	superscalar, Thread Level Parallelism, Multithreaded architectures, decoupled architectures, dataflow architectures
30	Joanna Bryson, Lynn Andrea Stein	Modularity and Specialized Learning: Mapping between Agent Architectures and Brain Organization.	Emergent Neural Computational Architectures Based on Neuroscience	2001	DBLP DOI BibTeX RDF	Structural and Temporal Modularity, Complete Autonomous Agents, Behavior-Based AI, Brain Organization, Action Selection and Synchronization, Perceptual, Episodic and Semantic Memory, Spatial
30	Samuil Angelov, Paul W. P. J. Grefen, Danny Greefhorst	A classification of software reference architectures: Analyzing their success and effectiveness.	WICSA/ECSA	2009	DBLP DOI BibTeX RDF
30	Ah Chung Tsoi	Recurrent Neural Network Architectures: An Overview.	Summer School on Neural Networks	1997	DBLP DOI BibTeX RDF
30	John Hannan	Operational Semantics-Directed Compilers and Machine Architectures.	ACM Trans. Program. Lang. Syst.	1994	DBLP DOI BibTeX RDF	pass separation, semantics-based compilation, abstract machines
30	Philip Heidelberger, M. Seetha Lakshmi	A Performance Comparison of Multi-Micro and Mainframe Database Architectures.	SIGMETRICS	1987	DBLP DOI BibTeX RDF
30	JongSoo Park, William J. Dally	Buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures.	SPAA	2010	DBLP DOI BibTeX RDF	compiler and tools for concurrent programming, green computing and power-efficient architectures, multi-core architectures, stream programming
30	Marco Ferretti	Multi-Media Extensions in Super-Pipelined Micro-Architectures. A New Case for SIMD Processing?	CAMP	2000	DBLP DOI BibTeX RDF	super-pipelined microarchitectures, general purpose microprocessors, Von-Neumann paradigm, image processing, parallel architectures, associated memory, instruction set architectures, massively parallel processors, multimedia extensions, SIMD processing
30	Roberto R. Osorio, Javier D. Bruguera	New arithmetic coder/decoder architectures based on pipelining.	ASAP	1997	DBLP DOI BibTeX RDF	arithmetic coder/decoder architectures, arithmetic encoding, arithmetic decoding, multilevel images, cycle length, VLSI, pipelining, VLSI architectures
30	Jing-Chiou Liou, Michael A. Palis	CASS: an efficient task management system for distributed memory architectures.	ISPAN	1997	DBLP DOI BibTeX RDF	CASS, granularity optimization, parallel algorithm, parallelism, compiler, parallel architectures, operating system, task scheduling, task management, distributed memory architectures
30	Lukasz Strozek, David M. Brooks	Energy- and area-efficient architectures through application clustering and architectural heterogeneity.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	Efficient custom architectures, heterogeneous ISA processors
30	Jaehong Park, Ravi S. Sandhu, J. Schifalacqua	Security Architectures for Controlled Digital Information Dissemination.	ACSAC	2000	DBLP DOI BibTeX RDF	controlled digital information dissemination, application-level security, use control, control set, distribution style, cryptography, virtual machine, watermarking, security of data, business data processing, information dissemination, security architectures, business, copy protection
30	Chandra Shekhar 0001, Raj Singh, A. S. Mandal, S. C. Bose, Ravi Saini, Pramod Tanwar	Application Specific Instruction Set Processors: Redefining Hardware-Software Boundary.	VLSI Design	2004	DBLP DOI BibTeX RDF
29	Jesper Berthing, Thomas Maier	A Taxonomy for Modelling Safety Related Architectures in Compliance with Functional Safety Requirements.	SAFECOMP	2007	DBLP DOI BibTeX RDF	dependable architectures, safety related architectures, IEC61508
29	Danilo Ardagna, Chiara Francalanci	A cost-oriented methodology for the design of web based IT architectures.	SAC	2002	DBLP DOI BibTeX RDF	IT architectures, web architectures, cost minimization
29	Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin	Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	area time trade-offs, micro-grain VLSI array architectures, massively parallel control-flow architectures, associative memory architecture, Mux-based SIMD architecture, systolic MIMD/MISD computation, data-flow requirements, performance evaluation, performance, VLSI, parallel architectures, FFT, matrix multiplication, RAMs
29	Patrick W. Dowd, Kalyani Bogineni, Khaled A. Aly, James A. Perreault	Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	photonic architectures, optical structures, processor interconnection, single-hop, optical fiber communication, parallel architectures, discrete-event simulation, discrete event simulation, analytic models, wavelength division multiplexing, wavelength division multiplexing, optical interconnections, hierarchical, parallel computer architecture, hierarchical architectures
28	Wolfgang Karl	Some Design Aspects for VLIW Architectures Exploiting Fine - Grained Parallelism.	PARLE	1993	DBLP DOI BibTeX RDF
28	Yahya Jan, Lech Józwiak	CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
28	Yahya Jan, Lech Józwiak	Survey of Advanced CABAC Accelerator Architectures for Future Multimedia.	ARC	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
28	Claudia Canali, Sara Casolari, Riccardo Lancellotti	Architectures for scalable and flexible Web personalization services.	AAA-IDEA	2005	DBLP DOI BibTeX RDF	Web content adaptation, High performance architectures, Web content delivery
28	Alfred Zimmermann, Rainer Schmidt 0001, Kurt Sandkuhl, Eman El-Sheikh, Dierk Jugel, Christian M. Schweda, Michael Möhring, Matthias Wißotzki, Birger Lantow	Leveraging Analytics for Digital Transformation of Enterprise Services and Architectures.	Emerging Trends in the Evolution of Service-Oriented and Enterprise Architectures	2016	DBLP DOI BibTeX RDF
28	Michael Gebhart, Pascal Giessler, Sebastian Abeck	Flexible and Maintainable Service-Oriented Architectures with Resource-Oriented Web Services.	Emerging Trends in the Evolution of Service-Oriented and Enterprise Architectures	2016	DBLP DOI BibTeX RDF
28	Eman El-Sheikh, Alfred Zimmermann, Lakhmi C. Jain	Evolution of Service-Oriented and Enterprise Architectures: An Introduction.	Emerging Trends in the Evolution of Service-Oriented and Enterprise Architectures	2016	DBLP DOI BibTeX RDF
28	Iván Contreras, José Ignacio Hidalgo, Laura Núñez-Letamendia, Yiyi Jiang	Parallel Architectures for Improving the Performance of a GA Based Trading System.	Parallel Architectures and Bioinspired Algorithms	2012	DBLP DOI BibTeX RDF
28	Marianne J. Jantz, Prasad A. Kulkarni	Understand and categorize dynamically dead instructions for contemporary architectures.	Interaction between Compilers and Computer Architectures	2012	DBLP DOI BibTeX RDF
28	Ahmed Al-Maashri, Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Narayanan Vijaykrishnan	Influence of Stacked 3D Memory/Cache Architectures on GPUs.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
28	Shan Yan, Bill Lin 0001	Design of Application-Specific 3D Networks-on-Chip Architectures.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
28	Jon G. Hall, John Grundy 0001, Ivan Mistrík, Patricia Lago, Paris Avgeriou	Introduction: Relating Requirements and Architectures.	Relating Software Requirements and Architectures	2011	DBLP DOI BibTeX RDF
28	Luciano Baresi, Liliana Pasquale	Adaptation Goals for Adaptive Service-Oriented Architectures.	Relating Software Requirements and Architectures	2011	DBLP DOI BibTeX RDF
28	Carlos Kavka, Luka Onesti, Enrico Rigoni, Alessandro Turco, Sara Bocchio, Fabrizio Castro, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria, Giovanni Mariani, Dongrui Fan, Hao Zhang 0009, Shibin Tang	Design Space Exploration of Parallel Architectures.	Multi-objective Design Space Exploration of Multiprocessor SoC Architectures	2011	DBLP DOI BibTeX RDF
28	Peter M. Athanas, Jürgen Becker 0001, Jürgen Teich, Ingrid Verbauwhede	10281 Abstracts Collection - Dynamically Reconfigurable Architectures.	Dynamically Reconfigurable Architectures	2010	DBLP BibTeX RDF
28	Peter M. Athanas, Jürgen Becker 0001, Jürgen Teich, Ingrid Verbauwhede	10281 Summary - Dynamically Reconfigurable Architectures.	Dynamically Reconfigurable Architectures	2010	DBLP BibTeX RDF
28	Matthias Hanke, Tim Kranich, Mladen Berekovic, Yannis Papaefstathiou	Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes.	Dynamically Reconfigurable Architectures	2010	DBLP BibTeX RDF
28	Karl Cheng-Heng Fua, Ian Horswill, Andrew Ortony, William Revelle	Reinforcement Sensitivity Theory and Cognitive Architectures.	AAAI Fall Symposium: Biologically Inspired Cognitive Architectures	2009	DBLP BibTeX RDF
28	Matthew Klenk	Transfer as a Benchmark for Multi-Representational Architectures.	AAAI Fall Symposium: Multi-Representational Architectures for Human-Level Intelligence	2009	DBLP BibTeX RDF
28	Steven Brian Morphet	An Engineering View of Cognitive Architectures.	AAAI Fall Symposium: Biologically Inspired Cognitive Architectures	2009	DBLP BibTeX RDF
28	Gary Berg-Cross	Emergently Developed Cognitive Architectures: Testing by Developmental Robotics.	AAAI Fall Symposium: Biologically Inspired Cognitive Architectures	2009	DBLP BibTeX RDF
28	Annie A. M. Cuyt, Walter Krämer, Wolfram Luther, Peter W. Markstein	08021 Summary - Numerical Validation in Current Hardware Architectures.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
28	Wolfram Luther, Annie A. M. Cuyt, Walter Krämer, Peter W. Markstein	08021 Abstracts Collection - Numerical Validation in Current Hardware Architectures.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
28	Rodrigo Ventura 0001	Action and Adaptation: Lessons from Neurobiology and Challenges for Robot Cognitive Architectures.	AAAI Fall Symposium: Biologically Inspired Cognitive Architectures	2008	DBLP BibTeX RDF
28	Stephen Grossberg	Towards Self-Organizing Autonomous Brain-Inspired Cognitive Architectures.	AAAI Fall Symposium: Biologically Inspired Cognitive Architectures	2008	DBLP BibTeX RDF
28	Claudius Gros, Gregor Kaczor	Evolving Complete Cognitive Architectures: The Role of Neural Competition and Diffusive Emotional Control for Learning and Emergent Cognitive Capabilities.	AAAI Fall Symposium: Biologically Inspired Cognitive Architectures	2008	DBLP BibTeX RDF
28	Jürgen Nehmer, Thomas Kleinberger	07462 Summary -- Assisted Living Systems - Models, Architectures and Engineering Approaches.	Assisted Living Systems - Models, Architectures and Engineering Approaches	2007	DBLP BibTeX RDF
28	Arthur I. Karshmer, Jürgen Nehmer, Hartmut Raffler, Gerhard Tröster	07462 Abstracts Collection -- Assisted Living Systems - Models, Architectures and Engineering Approaches.	Assisted Living Systems - Models, Architectures and Engineering Approaches	2007	DBLP BibTeX RDF
28	Mihai Barbuceanu, Rune Teigen	Higher Level Integration by Multi-Agent Architectures.	Handbook on Architectures of Information Systems	2006	DBLP DOI BibTeX RDF
28	Rainer Buchty	Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Frank Leymann, Wolfgang Reisig, Satish R. Thatte, Wil M. P. van der Aalst	06291 Abstracts Collection -- The Role of Business Processes in Service-Oriented Architectures.	The Role of Business Processes in Service Oriented Architectures	2006	DBLP BibTeX RDF
28	Jürgen Becker 0001, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas	06141 Abstracts Collection -- Dynamically Reconfigurable Architectures.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Jürgen Becker 0001, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas	06141 Executive Summary -- Dynamically Reconfigurable Architectures.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal, Paul M. Heysters	Efficient architectures for streaming applications.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Erik R. Altman, James C. Dehnert, Christoph W. Kessler, Jens Knoop	05101 Executive Summary - Scheduling for Parallel Architectures: Theory, Applications, Challenges.	Scheduling for Parallel Architectures	2005	DBLP BibTeX RDF
28	Erik R. Altman, James C. Dehnert, Christoph W. Kessler, Jens Knoop	05101 Abstracts Collection - Scheduling for Parallel Architectures: Theory, Applications, Challenges.	Scheduling for Parallel Architectures	2005	DBLP BibTeX RDF
28	Carlos Molina, Antonio González 0001, Jordi Tubella	Compiler analysis for trace-level speculative multithreaded architectures.	Interaction between Compilers and Computer Architectures	2005	DBLP DOI BibTeX RDF
28	Michael J. Wooldridge, Nicholas R. Jennings	Agent Theories, Architectures, and Languages: A Survey.	ECAI Workshop on Agent Theories, Architectures, and Languages	1994	DBLP DOI BibTeX RDF
28	Jörg P. Müller, Markus Pischel, Michael Thiel	Modelling Reactive Behaviour in Vertically Layered Agent Architectures.	ECAI Workshop on Agent Theories, Architectures, and Languages	1994	DBLP DOI BibTeX RDF
28	Jack J. Stiffler	Fault Tolerant Architectures - Past, Present, and (?) Future.	Hardware and Software Architectures for Fault Tolerance	1993	DBLP DOI BibTeX RDF
28	David A. Berson, Rajiv Gupta 0001, Mary Lou Soffa	URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures.	Architectures and Compilation Techniques for Fine and Medium Grain Parallelism	1993	DBLP BibTeX RDF
28	G. Menez, Michel Auguin, Fernand Boéri, C. Carrière	Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW Architectures.	Architectures and Compilation Techniques for Fine and Medium Grain Parallelism	1993	DBLP BibTeX RDF
28	Stephan Murer, Philipp Färber	Code Generation for Multi-Threaded Architectures from Dataflow Graphs.	Architectures and Compilation Techniques for Fine and Medium Grain Parallelism	1993	DBLP BibTeX RDF
28	Henning Spruth, Frank M. Johannes	Architectures for Parallel Slicing Enumeration in VLSI Layout.	Parallel Computer Architectures	1993	DBLP DOI BibTeX RDF
28	Patrice Quinton, Yves Robert (eds.)	Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991	Algorithms and Parallel VLSI Architectures	1992	DBLP BibTeX RDF
28	Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes	Generalized cycle shrinking.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Jingling Xue, Christian Lengauer	Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Selim G. Akl, John M. Calvert, Ivan Stojmenovic	Systolic generation of derangements.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	John G. McWhirter, Ian K. Proudler	Orthogonal lattice algorithms for adaptive filtering and beamforming.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	M. Van Swaalj, Francky Catthoor, Hugo De Man	Signal analysis and signal transformations for ASIC regular array architecture synthesis.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Sanjay V. Rajopadhye	An improved systolic algorithm for the algebraic path problem.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Mokhtar Aboelaze, De-Lei Lee, Benjamin W. Wah	A programmable VLSI array with constant I/O pins.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Catherine Dezan, Hervé Le Verge, Patrice Quinton, Yannick Saouter	The Alpha du Centaur environment.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Tanguy Risset	Linear systolic arrays for matrix multiplication: comparisons of existing synthesis methods and new results.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Frédéric Rocheteau, Nicolas Halbwachs	POLLUS: A LUSTRE based hardware design environment.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Alle-Jan van der Veen, Patrick M. Dewilde	Time-varying system theory for computational networks.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Frédéric Dufaux, Murat Kunt	Matrix Multiplication on an associative string processor: application to image compression by Gabor expansion.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Rumen Andonov, Frédéric Gruau	A 2D toroidal systolic array for the knapsack problem.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Ravi Varadarajan, Bhavani Ravichandran	Refinement based algorithm mapping techniques for linear systolic arrays.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch	Synthesis of intermediate memories for the data supply to processor arrays.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Alain Darte	Two heuristics for task scheduling.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Dimitrios Soudris, Michael K. Birbas, Constantinos E. Goutis	Direct mapping of nested loops on piecewise regular processor arrays.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Vincent Van Dongen	From systolic to periodic array design.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Paul Le Guernic	The SIGNAL programming environment.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Frank K. H. A. Dehne, Andrew Rau-Chaplin	Parallel algorithms for color image quantization on hypercubes and meshes.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Uwe Vehlies	The derivation of dependence graphs from PASCAL programs for array processor design.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Mohammad Shakeel Laghari, Farzin Deravi	Comparison of scheduling techniques for the parallel implementation of the Hough transform.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Francky Catthoor, M. Van Swaalj, Jan Rosseel, Hugo De Man	Array design methodologies for real-time signal processing in the CATHEDRAL-IV synthesis environment.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF
28	Gur Saran Adhar, Shietung Peng	Parallel algorithms for finding connected, independent and total domination in interval graphs.	Algorithms and Parallel VLSI Architectures	1991	DBLP BibTeX RDF