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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 24 occurrences of 21 keywords
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Results
Found 24 publication records. Showing 24 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
76 | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
Parallel fault backtracing for calculation of fault coverage. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
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64 | Ohyoung Song, Premachandran R. Menon |
3-valued trace-based fault simulation of synchronous sequential circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
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55 | Kameshwar Chandrasekar, Michael S. Hsiao |
Forward image computation with backtracing ATPG and incremental state-set construction. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
model checking, ATPG, image computation, ZBDDs |
43 | Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui |
PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits. |
ISMVL |
2002 |
DBLP DOI BibTeX RDF |
Static Testability Measures, Dynamic Testability Measures, Test Generation, Multiple-Valued Logic, PODEM |
43 | Ramakrishna Voorakaranam, Abhijit Chatterjee |
Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test. |
ARVLSI |
1999 |
DBLP DOI BibTeX RDF |
analog verification, fault diagnosis, test generation, analog testing, Backtrace |
33 | Rose E. Wang, Pawan Wirawarn, Omar Khattab, Noah D. Goodman, Dorottya Demszky |
Backtracing: Retrieving the Cause of the Query. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
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33 | Rose E. Wang, Pawan Wirawarn, Omar Khattab, Noah D. Goodman, Dorottya Demszky |
Backtracing: Retrieving the Cause of the Query. |
EACL (Findings) |
2024 |
DBLP BibTeX RDF |
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33 | Jingwen Chen, Jianjie Luo, Yingwei Pan, Yehao Li, Ting Yao, Hongyang Chao, Tao Mei 0001 |
Boosting Vision-and-Language Navigation with Direction Guiding and Backtracing. |
ACM Trans. Multim. Comput. Commun. Appl. |
2023 |
DBLP DOI BibTeX RDF |
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33 | Benjamin Paaßen |
Revisiting the tree edit distance and its backtracing: A tutorial. |
CoRR |
2018 |
DBLP BibTeX RDF |
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33 | Jianming Fu, Xinwen Liu 0002, Binling Cheng |
Malware Behavior Capturing Based on Taint Propagation and Stack Backtracing. |
TrustCom |
2011 |
DBLP DOI BibTeX RDF |
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33 | Dario V. Forte |
Advances in Onion Routing: Description and backtracing/investigation problems. |
Digit. Investig. |
2006 |
DBLP DOI BibTeX RDF |
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33 | Dario V. Forte |
Analyzing the Difficulties in Backtracing Onion Router Traffic. |
Int. J. Digit. EVid. |
2002 |
DBLP BibTeX RDF |
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33 | Gabriel M. Silberman, Ilan Y. Spillinger |
A backtracing-oriented procedure for the analysis of combinational gate-level designs. |
Integr. |
1994 |
DBLP DOI BibTeX RDF |
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33 | Gabriel M. Silberman, Ilan Y. Spillinger |
G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing. |
ITC |
1988 |
DBLP DOI BibTeX RDF |
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33 | Michael L. Bushnell, John Giraldi |
A Functional Decomposition Method for Redundancy Identification and Test Generation. |
J. Electron. Test. |
1997 |
DBLP DOI BibTeX RDF |
redundancy identification, logic testing, automatic test generation, backtracing |
33 | Gabriel M. Silberman, Ilan Y. Spillinger |
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation. |
IEEE Trans. Computers |
1991 |
DBLP DOI BibTeX RDF |
functional fault simulation, biased-random test pattern generation, implementation-level faults, functional-level description, combinational VLSI design, difference fault model, formal abstraction, nonuniformly random test patterns, backtracing process, VLSI, logic testing, fault simulation, fault location, combinatorial circuits, functional fault model |
21 | King Leong Lee, Nadir Z. Basturkmen, Srikanth Venkataraman |
Diagnosis of Scan Clock Failures. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
scan clock, diagnosis, scan chain |
21 | Rajesh Ramadoss, Michael L. Bushnell |
Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. |
J. Electron. Test. |
1999 |
DBLP DOI BibTeX RDF |
analog test generation, mixed-signal test generation, back tracing, parametric faults, catastrophic faults |
21 | Eric McCreath, Mark D. Reid |
A Noise Resistant Model Inference System. |
Discovery Science |
1999 |
DBLP DOI BibTeX RDF |
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21 | Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer |
SWiTEST: a switch level test generation system for CMOS combinational circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
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21 | Hyoung B. Min, Hwei-Tsu Ann Luh, William A. Rogers |
Hierarchical test pattern generation: a cost model and implementation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
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21 | Ohyoung Song, Premachandran R. Menon |
Acceleration of trace-based fault simulation of combinational circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
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21 | Hiroki Ishizaka |
Inductive Inference of Regular Language Based on Model Inference. |
LP |
1987 |
DBLP DOI BibTeX RDF |
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21 | Susheel J. Chandra, Janak H. Patel |
A Hierarchical Approach Test Vector Generation. |
DAC |
1987 |
DBLP DOI BibTeX RDF |
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