Search results for "billion-transistor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
58	Doug Burger, James R. Goodman	Billion-Transistor Architectures: There and Back Again.	Computer	2004	DBLP DOI BibTeX RDF
57	Sek M. Chai, Antonio Gentile, D. Scott Wills	Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor.	ARVLSI	1999	DBLP DOI BibTeX RDF	billion-transistor, image processing, technology, SIMD, system modeling, parallel computer architecture, Power density, focal plane
43	Nikil D. Dutt	Quo vadis, BTSoC (Billion Transistor SoC)?	ASP-DAC	2008	DBLP DOI BibTeX RDF
43	Lucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl	Exploring Microprocessor Architectures for Gigascale Integration.	ARVLSI	1999	DBLP DOI BibTeX RDF	Billion Transistor, Future Tecnologies, Architecture, Microprocessors
33	Xin Fu, Tao Li, José A. B. Fortes	Soft error vulnerability aware process variation mitigation.	HPCA	2009	DBLP DOI BibTeX RDF
32	Steve B. Furber	Living with Failure: Lessons from Nature?	ETS	2006	DBLP DOI BibTeX RDF
30	Stanislav Sedukhin, Mostafa I. Soliman	Trident: Technology-Scalable Architecture for Data Parallel Application.	IPDPS	2003	DBLP DOI BibTeX RDF	scalar/vector/matrix processing, data parallel applications, scalable architecture, BLAS
28	Reid J. Riedlinger, Ron Arnold, Larry Biro, William J. Bowhill, Jason Crop, Kevin Duda, Eric S. Fetzer, Olivier Franza, Tom Grutkowski, Casey Little, Charles Morganti, Gary Moyer, Ashley O. Munch, Mahalingam Nagarajan, Cheolmin Park, Christopher Poirier, Bill Repasky, Edi Roytman, Tejpal Singh, Matthew W. Stefaniw	A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
28	Reid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski	A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers.	ISSCC	2011	DBLP DOI BibTeX RDF
28	Blaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer	A 65 nm 2-Billion Transistor Quad-Core Itanium Processor.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
28	Blaine A. Stackhouse, Brian S. Cherkauer, Michael K. Gowan, Paul E. Gronowski, Chris Lyles	A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor.	ISSCC	2008	DBLP DOI BibTeX RDF
28	Yuhua Chen	Cell Switched Network-on-Chip - Candidate for Billion-Transistor System-on-Chips.	SoCC	2006	DBLP DOI BibTeX RDF
28	Dileep Bhandarkar	Billion Transistor Chips in Mainstream Enterprise Platforms of the Future.	HPCA	2003	DBLP DOI BibTeX RDF
28	Patrick Groeneveld	Physical Design Challenges for Billion Transistor Chips.	ICCD	2002	DBLP DOI BibTeX RDF
28	Jason Fritts, Zhao Wu, Wayne H. Wolf	Parallel Media Processors for the Billion-Transistor Era.	ICPP	1999	DBLP DOI BibTeX RDF	PMP, billion transistors, cluster scheduling, parallel architecture, data partitioning, media processor
28	Robert C. Aitken, Jason Cong, Randy Harr, Kenneth L. Shepard, Wayne H. Wolf	How will CAD handle billion-transistor systems? (panel).	ICCAD	1998	DBLP DOI BibTeX RDF
28	Doug Burger, James R. Goodman	Billion-Transistor Architectures - Guest Editors' Introduction.	Computer	1997	DBLP DOI BibTeX RDF
28	Christoforos E. Kozyrakis, Stylianos Perissakis, David A. Patterson 0001, Thomas E. Anderson, Krste Asanovic, Neal Cardwell, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Randi Thomas, Noah Treuhaft, Katherine A. Yelick	Scalable Processors in the Billion-Transistor Era: IRAM.	Computer	1997	DBLP DOI BibTeX RDF
24	Mahdiar Hosein Ghadiry, Mahdieh Nadi Senjani, M. T. Manzuri-Shalmani, Dara Rahmati	Effect of number of faults on NoC power and performance.	ICPADS	2007	DBLP DOI BibTeX RDF
15	Dan Zhao 0001, Yi Wang 0007	MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
15	Tyrone Tai-On Kwok, Yu-Kwong Kwok	On the design, control, and use of a reconfigurable heterogeneous multi-core system-on-a-chip.	IPDPS	2008	DBLP DOI BibTeX RDF
15	Nicholas Allec, Zyad Hassan, Li Shang, Robert P. Dick, Ronggui Yang	ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
15	Xingzhi Wen, Uzi Vishkin	Fpga-based prototype of a pram-on-chip processor.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	ease-of-programming, explicit multi-threading, on-chip parallel processor, pram, parallel algorithms, xmt
15	Shuo Wang, Lei Wang 0003	Design of error-tolerant cache memory for multithreaded computing.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Jan M. Rabaey	Design Without Borders.	DSD	2007	DBLP DOI BibTeX RDF
15	Chang-Burm Cho, Wangyuan Zhang, Tao Li 0006	Informed Microarchitecture Design Space Exploration Using Workload Dynamics.	MICRO	2007	DBLP DOI BibTeX RDF
15	Yi Wang 0007, Dan Zhao 0001	Design and Implementation of Routing Scheme for Wireless Network-on-Chip.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Marcal Pol	Self-Adaptive Systems to Drive out the Nano-Scale Devil.	ISQED	2007	DBLP DOI BibTeX RDF
15	Jan M. Rabaey	Design without Borders - A Tribute to the Legacy of A. Richard Newton.	DAC	2007	DBLP BibTeX RDF
15	Per Stenström	Chip-multiprocessing and beyond.	HPCA	2006	DBLP DOI BibTeX RDF
15	Robert D. Mullins, Andrew West, Simon W. Moore	The design and implementation of a low-latency on-chip network.	ASP-DAC	2006	DBLP DOI BibTeX RDF
15	Raj Varada, Mysore Sriram, Kris Chou, James Guzzo	Design and integration methods for a multi-threaded dual core 65nm Xeon® processor.	ICCAD	2006	DBLP DOI BibTeX RDF	Xeon®, Integration, Design Methods, processor
15	Seong-Won Lee, Neungsoo Park, Jean-Luc Gaudiot	Low Power Microprocessor Design for Embedded Systems.	ICCSA (4)	2006	DBLP DOI BibTeX RDF
15	Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter	Interconnect-Aware Coherence Protocols for Chip Multiprocessors.	ISCA	2006	DBLP DOI BibTeX RDF
15	Andrew B. Kahng	CAD challenges for leading-edge multimedia designs.	DAC	2006	DBLP DOI BibTeX RDF
15	Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy	Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
15	Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin	Exploiting Barriers to Optimize Power Consumption of CMPs.	IPDPS	2005	DBLP DOI BibTeX RDF
15	Sudeep Pasricha, Mohamed Ben-Romdhane	Using TLM for Exploring Bus-based SoC Communication Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
15	Xi Chen 0024, Harry Hsieh, Felice Balarin, Yosinori Watanabe	Logic of constraints: a quantitative performance and functional constraint formalism.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
15	Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar	Min-cut program decomposition for thread-level speculation.	PLDI	2004	DBLP DOI BibTeX RDF	partitioning, chip multiprocessor, thread-level speculation, min-cut, program decomposition
15	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	A Scalable Communication-Centric SoC Interconnect Architecture.	ISQED	2004	DBLP DOI BibTeX RDF	switch-based interconnect, butterfly fat-tree, global wire delay, System on chip, interconnect architecture, timing closure
15	Jörg Henkel, Wayne H. Wolf, Srimat T. Chakradhar	On-chip networks: A scalable, communication-centric embedded system design paradigm.	VLSI Design	2004	DBLP DOI BibTeX RDF
15	Rob A. Rutenbar, Anthony R. Bonaccio, Teresa H. Meng, Ernesto Perea, Robert Pitts, Charles G. Sodini, Jim Wieser	Will Moore's Law rule in the land of analog?	DAC	2004	DBLP DOI BibTeX RDF
15	César Albenes Zeferino, Altamiro Amadeu Susin	SoCIN: A Parametric and Scalable Network-on-Chip.	SBCCI	2003	DBLP DOI BibTeX RDF	FPGA, Embedded Systems, Systems-on-Chip
15	Michael D. Powell, T. N. Vijaykumar	Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise.	ISLPED	2003	DBLP DOI BibTeX RDF	a priori current ramping, pipeline muffling, leakage, decoupling capacitors, inductive noise
15	Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh	Design of a switch for network on chip applications.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
15	Dan Zhao 0001, Shambhu J. Upadhyaya, Martin Margala	Control Constrained Resource Partitioning for Complex SoCs.	DFT	2003	DBLP DOI BibTeX RDF
15	Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar	Extending Platform-Based Design to Network on Chip Systems.	VLSI Design	2003	DBLP DOI BibTeX RDF
15	Partha Pratim Pande, Cristian Grecu, André Ivanov	High-Throughput Switch-Based Interconnect for Future SoCs.	IWSOC	2003	DBLP DOI BibTeX RDF	SoC, Wormhole Routing, Virtual Channels, Interconnect Architecture
15	Mohamed Shalan, Vincent John Mooney III	Hardware support for real-time embedded multiprocessor system-on-a-chip memory management.	CODES	2002	DBLP DOI BibTeX RDF	Atalanta, SoCDMMU, real-time operating systems., two-level memory management, real-time systems, embedded systems, System-on-a-Chip, dynamic memory management
15	Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis	Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects.	ICCAD	2002	DBLP DOI BibTeX RDF
15	Tuomas Valtonen, Tero Nurmi, Jouni Isoaho, Hannu Tenhunen	Interconnection of autonomous error-tolerant cells.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
15	Abby A. Ilumoka	Chip Level Signal Integrity Analysis & Crosstalk Prediction Using Artificial Neural Nets.	ISQED	2002	DBLP DOI BibTeX RDF
15	Uzi Vishkin	What to Do with All this Hardware? (Invited Lecture).	CPM	2001	DBLP DOI BibTeX RDF
15	Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl	A compact physical via blockage model.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
15	John A. Darringer, Evan E. Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich C. Schanzenbach, Gustavo E. Téllez, Louise Trevillyan	EDA in IBM: past, present, and future.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
15	Hugo De Man	System-on-Chip Design: Impact on Education and Research.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
15	Michael Nicolaidis, Yervant Zorian	Scaling Deeper to Submicron: On-Line Testing to the Rescue.	DATE	1999	DBLP DOI BibTeX RDF
15	Francesco Pessolano	Heterogeneous Clustered Processors: Organisation and Design.	Euro-Par	1999	DBLP DOI BibTeX RDF