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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 17 occurrences of 12 keywords
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Results
Found 20 publication records. Showing 20 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
78 | Alexander Zelikovsky, Ion I. Mandoiu |
Practical approximation algorithms for zero- and bounded-skew trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Twelfth Annual Symposium on Discrete Algorithms, January 7-9, 2001, Washington, DC, USA., pp. 407-416, 2001, ACM/SIAM, 0-89871-490-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
73 | Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao |
Bounded-skew clock and Steiner routing under Elmore delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 66-71, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
bounded-skew, pathlength delay, VLSI, global routing, Elmore delay, zero-skew, zero-skew, clock routing, routing trees |
71 | Chung-Wen Albert Tsao, Cheng-Kok Koh |
UST/DME: a clock tree router for general skew constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(3), pp. 359-379, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Useful Skew, feasible skew range, incremental skew scheduling, merging and embedding, merging region, clock tree |
44 | Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao |
Bounded-skew clock and Steiner routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(3), pp. 341-388, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
(inter)connection, boundary merging and embedding, bounded-skew, interior merging and embedding, merging region, merging segment, pathlength delay, VLSI, low power, synchronization, Steiner tree, clock tree, Elmore delay, zero-skew |
41 | Hyo Jung Song, Andrew A. Chien |
Feedback-Based Synchronization in System Area Networks for Cluster Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(10), pp. 908-920, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
link level flow control, Synchronization, cluster computing, system area networks |
30 | Tak-Yung Kim, Taewhan Kim |
Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Green Computing Conference ![In: International Green Computing Conference 2010, Chicago, IL, USA, 15-18 August 2010, pp. 525-532, 2010, IEEE Computer Society, 978-1-4244-7612-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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30 | Vinayak Honkote, Baris Taskin |
Skew analysis and bounded skew constraint methodology for rotary clocking technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 11th International Symposium on Quality of Electronic Design (ISQED 2010), 22-24 March 2010, San Jose, CA, USA, pp. 413-417, 2010, IEEE, 978-1-4244-6455-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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19 | Hamed Fatemi, Andrew B. Kahng, Minsoo Kim, José Pineda de Gyvez |
Optimal bounded-skew steiner trees to minimize maximum k-active dynamic power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop, San Diego, California, November 5, 2020, pp. 12, 2020, ACM, 978-1-4503-8106-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Jianchao Lu, Vinayak Honkote, Xin Chen, Baris Taskin |
Steiner tree based rotary clock routing with bounded skew and capacitive load balancing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 455-460, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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19 | Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino |
Thermal resilient bounded-skew clock tree optimization methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 832-837, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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19 | Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili |
Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10), pp. 1637-1643, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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19 | Moses Charikar, Jon M. Kleinberg, Ravi Kumar 0001, Sridhar Rajagopalan, Amit Sahai, Andrew Tomkins |
Minimizing Wirelength in Zero and Bounded Skew Clock Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIAM J. Discret. Math. ![In: SIAM J. Discret. Math. 17(4), pp. 582-595, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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19 | Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili |
Adaptive wire adjustment for bounded skew Clock Distribution Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 243-248, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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19 | Alexander Zelikovsky, Ion I. Mandoiu |
Practical Approximation Algorithms for Zero- and Bounded-Skew Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIAM J. Discret. Math. ![In: SIAM J. Discret. Math. 15(1), pp. 97-111, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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19 | Moses Charikar, Jon M. Kleinberg, Ravi Kumar 0001, Sridhar Rajagopalan, Amit Sahai, Andrew Tomkins |
Minimizing Wirelength in Zero and Bounded Skew Clock Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Tenth Annual ACM-SIAM Symposium on Discrete Algorithms, 17-19 January 1999, Baltimore, Maryland, USA., pp. 177-184, 1999, ACM/SIAM, 0-89871-434-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP BibTeX RDF |
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19 | Andrew B. Kahng, Chung-Wen Albert Tsao |
Practical Bounded-Skew Clock Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 16(2-3), pp. 199-215, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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19 | Andrew B. Kahng, Chung-Wen Albert Tsao |
More Practical Bounded-Skew Clock Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 594-599, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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19 | Jason Cong, Cheng-Kok Koh |
Minimum-Cost Bounded-Skew Clock Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 215-218, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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19 | Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Albert Tsao |
On the Bounded-Skew Clock and Steiner Routing Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995., pp. 508-513, 1995, ACM Press, 0-89791-725-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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11 | Jean Mayo, Phil Kearns |
Distributed Deadlock Detection and Resolution Based on Hardware Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: Proceedings of the 19th International Conference on Distributed Computing Systems, Austin, TX, USA, May 31 - June 4, 1999, pp. 208-215, 1999, IEEE Computer Society, 0-7695-0222-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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