|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 26 occurrences of 22 keywords
|
|
|
Results
Found 51 publication records. Showing 51 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
106 | Günter Knittel |
Pipelined Bus-Invert Coding for FPGAs Driving High-Speed DDR-Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 1131-1136, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bus-Invert Coding, Dual-Data-Rate, FPGA |
103 | Sharath Jayaprakash, Nihar R. Mahapatra |
Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 127-134, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
93 | Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi |
Partial bus-invert coding for power optimization of application-specific systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 377-383, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
88 | Rung-Bin Lin, Chi-Ming Tsai |
Theoretical analysis of bus-invert coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(6), pp. 929-934, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
77 | Rung-Bin Lin |
Coupling reduction analysis of bus-invert coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5862-5865, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
77 | Rung-Bin Lin, Chi-Ming Tsai |
Weight-Based Bus-Invert Coding for Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 121-125, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
71 | Shanq-Jang Ruan, Tsang-Chi Kan, Jih-Chieh Hsu |
A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 357-360, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
bus-invert, coupling, interconnect delay |
71 | Yan Zhang 0028, John C. Lach, Kevin Skadron, Mircea R. Stan |
Odd/even bus invert with two-phase transfer for buses with coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 80-83, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
bus invert, buses with coupling, coding for low-power I/O |
67 | Tina Lindkvist |
Additional Knowledge of Bus Invert Coding Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 301-303, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
64 | Jayapreetha Natesan, Damu Radhakrishnan |
Shift Invert Coding (SINV) for Low Power VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 190-194, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
64 | Tudor Murgan, Petru Bogdan Bacinschi, Alberto García Ortiz, Manfred Glesner |
Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 169-180, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
62 | Liang Deng, Martin D. F. Wong |
Energy optimization in memory address bus structure for application-specific systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 232-237, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
60 | Matheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger |
Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1372-1373, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
57 | Haris Lekatsas, Jörg Henkel, Wayne H. Wolf |
Approximate arithmetic coding for bus transition reduction in low power designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 696-707, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
54 | Unni Narayanan, Ki-Seok Chung, Taewhan Kim |
Enhanced bus invert encodings for low-power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 25-28, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
54 | Mircea R. Stan, Wayne P. Burleson |
Bus-invert coding for low-power I/O. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(1), pp. 49-58, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
51 | Vijay Sundararajan, Keshab K. Parhi |
Reducing bus transition activity by limited weight coding with codeword slimming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 13-16, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
50 | Jun Yang 0002, Rajiv Gupta 0001, Chuanjun Zhang |
Frequent value encoding for low power data buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(3), pp. 354-384, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching |
49 | K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas |
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 336-339, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Simultaneous Switching Noise (SSN), Odd Simultaneous Transitions (OST), Even Simultaneous Transitions (EST), VLSI, Low power, Coding |
46 | Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira |
Using Complementation and Resequencing to Minimize Transitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 694-697, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reconfigurable computing, event-driven simulation |
44 | Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001 |
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1225-1238, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4134-4137, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001 |
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 194-199, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | André K. Nieuwland, Atul Katoch, Daniele Rossi 0001, Cecilia Metra |
Coding Techniques for Low Switching Noise in Fault Tolerant Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 183-189, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Ji Gu, Hui Guo 0001 |
An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2009, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | Ji Gu, Hui Guo 0001 |
A Segmental Bus-invert Coding Method for Instruction Memory Data Bus Power Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 137-140, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | Myungchul Yoon, Byeong-Hee Roh |
A Novel Low-Power Bus Design for Bus-Invert Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 90-C(4), pp. 731-734, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi |
Partial bus-invert coding for power optimization of system level bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 127-129, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
40 | Haris Lekatsas, Jörg Henkel |
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 113-120, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
bus invert, low power, bus encoding |
34 | Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye |
Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 377-382, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram |
Software-Only Bus Encoding Techniques for an Embedded System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 126-131, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
memory bus encoding, bus activity minimization, CompactFlash, low power, Flash memory, LCD |
34 | Youngsoo Shin, Kiyoung Choi, Young-Hoon Chang |
Narrow bus encoding for low-power DSP systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(5), pp. 656-660, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos |
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.12691, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
31 | Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos |
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 12th International Conference on Modern Circuits and Systems Technologies, MOCAST 2023, Athens, Greece, June 28-30, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2107-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
31 | M. Ali Vosoughi, Longfei Wang, Selçuk Köse |
Bus-Invert Coding as a Low-Power Countermeasure Against Correlation Power Analysis Attack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2019, Las Vegas, NV, USA, June 1-2, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-2818-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
31 | Myungchul Yoon |
Achieving Maximum Performance for Bus-Invert Coding with Time-Splitting Transmitter Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12), pp. 2357-2363, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
31 | Melinda Y. Agyekum, Steven M. Nowick |
A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 1370-1375, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
31 | Ni Zhou, Fei Qiao, Huazhong Yang, Hui Wang 0004 |
Low-Power Off-Chip Memory Design for Video Decoder Using Embedded Bus-Invert Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISADS ![In: 10th International Symposium on Autonomous Decentralized Systems, ISADS 2011, Tokyo & Hiroshima, Japan, March 23-17, 2011, pp. 251-255, 2011, IEEE Computer Society, 978-1-61284-213-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
31 | Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys |
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 57-II(10), pp. 777-781, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
31 | Fakhrul Zaman Rokhani, Wen-Chih Kan, John C. Kieffer, Gerald E. Sobelman |
Optimality of Bus-Invert Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 55-II(11), pp. 1134-1138, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Rung-Bin Lin |
Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7), pp. 1911-1920, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Alberto Aloisio, Paolo Branchini |
Synchronous VME64x Block Transfers with Bus-Invert Coding For Low Noise, Low Power Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIIS ![In: IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, ICIIS 2008, Kharagpur, India, December 8-10, 2008, pp. 1-7, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Tudor Murgan, Andre Guntoro, Heiko Hinkelmann, Petru Bogdan Bacinschi, Manfred Glesner |
Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007, pp. 7-14, 2007, Univ. Montpellier II, 2-9517461-3-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
31 | Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung |
Decomposition of Bus-Invert Coding for Low-Power I/O. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 10(1-2), pp. 101-112, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou |
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2258-2264, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye |
Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1611-1614, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Enric Musoll, Tomás Lang, Jordi Cortadella |
Working-zone encoding for reducing the energy in microprocessor address buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(4), pp. 568-572, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
28 | Mircea R. Stan, Wayne P. Burleson |
Coding a terminated bus for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 70-73, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses |
18 | Fakhrul Zaman Rokhani, Gerald E. Sobelman |
Low-Power Bus Transform Coding for Multilevel Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1272-1275, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Information-theoretic bounds on average signal transition activity [VLSI systems]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(3), pp. 359-368, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Achievable bounds on signal transition activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 126-129, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
achievable bounds, busses, Low power, information theory, power estimation, CMOS circuits, switching activity |
Displaying result #1 - #51 of 51 (100 per page; Change: )
|
|