Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
126 | Vitit Kantabutra |
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(12), pp. 1495-1499, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
recursive carry-lookahead/carry-select hybrid adder, double-precision mantissas, spanning tree carry lookahead adder, redundant cell adder, Am29050 microprocessor, Manchester carry chains, delays, adders |
125 | Yu-Ting Pai, Yu-Kumg Chen |
The Fastest Carry Lookahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 434-436, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
central processing unit, integrated circuit, adder, gate delay, carry lookahead adder |
104 | Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald |
Self-Timed Carry-Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(7), pp. 659-672, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
delay-insenstive circuits, tree iterative circuits, CMOS, Self-timed circuits, carry-lookahead adders |
82 | Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis |
C-Testable modified-Booth multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 241-260, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model |
82 | Jin-Fu Li 0001, Jiunn-Der Yu, Yu-Jen Huang |
A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 77-80, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
80 | Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian |
Easily Testable Cellular Carry Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 285-298, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model |
80 | Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka |
A fast hybrid carry-lookahead/carry-select adder design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001, pp. 149-152, 2001, ACM, 1-58113-351-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
CMOS, domino logic, carry lookahead adder |
80 | Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija |
Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(8), pp. 920-930, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
delay optimisation, block carry-lookahead adders, multidimensional dynamic programming, worst-case carry propagation delays, minimum latency, fanin, dynamic programming, digital arithmetic, adders, gate delays, carry logic, fanout, critical path delay, carry-skip adders |
67 | Wen-Chang Yeh, Chein-Wei Jen |
Generalized Earliest-First Fast Addition Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(10), pp. 1233-1242, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Carry-propagation adder, final adder, conditional-sum, carry-lookahead |
67 | John P. Fishburn |
A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-between. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 361-364, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
64 | Tom Rhyne |
Limitations on Carry Lookahead Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(4), pp. 373-374, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
high-speed arithmetic, Binary addition, carry lookahead |
63 | Hussain Al-Asaad, John P. Hayes, Brian T. Murray |
Scalable Test Generators for High-Speed Datapath Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 111-125, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
datapath circuits, scalability, built-in self-test, test generation, on-line testing, carry lookahead |
62 | P. Balasubramanian 0001, Cuong Dang, Douglas L. Maskell, K. Prasad |
Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1710.05470, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
61 | Yijun Liu, Stephen B. Furber |
The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 647-656, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry |
High-performance carry chains for FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 138-147, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
52 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry |
High-Performance Carry Chains for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 223-233, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
48 | R. D. (Shawn) Blanton, John P. Hayes |
Design of a fast, easily testable ALU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 9-16, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit |
47 | Peter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López |
Low depth carry lookahead addition using charge recycling threshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 469-472, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
47 | Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang |
A 1.25 GHz 32-bit tree-structured carry lookahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 80-83, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
47 | Sae Hwan Kim, Shiu-Kai Chin |
Formal Verification of Tree-Structured Carry-Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 232-233, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
47 | Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho |
Delay-Insensitive Carry-Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 322-328, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
47 | Shobhit Belwal, Rajat Bhattacharjya, Kaustav Goswami 0002, Dip Sankar Banerjee |
ACLA: An Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 22nd International Symposium on Quality Electronic Design, ISQED 2021, Santa Clara, CA, USA, April 7-9, 2021, pp. 1-7, 2021, IEEE, 978-1-7281-7641-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
47 | Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, Yasmin Afsharnezhad, Elham Zahraie Salehi |
CL-CPA: A hybrid carry-lookahead/carry-propagate adder for low-power or high-performance operation mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 57, pp. 62-68, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
47 | P. Balasubramanian 0001, Cuong Dang, Douglas L. Maskell, K. Prasad |
Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1710.05474, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
47 | P. Balasubramanian 0001, Nikos E. Mastorakis |
ASIC-based Implementation of Synchronous Section-Carry Based Carry Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1603.07961, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
47 | P. Balasubramanian 0001, Nikos E. Mastorakis |
Design of Synchronous Section-Carry Based Carry Lookahead Adders with Improved Figure of Merit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1606.05621, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
47 | Atef Ibrahim, Fayez Gebali |
Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 46(9), pp. 783-794, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
47 | P. Balasubramanian 0001, David A. Edwards, William B. Toms |
Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 22(4), 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
47 | Habib Ghasemizadeh Tamar, Akbar Ghasemizadeh Tamar, Khayrollah Hadidi, Abdollah Khoei, Pourya Hoseini |
High speed area reduced 64-bit static hybrid carry-lookahead/carry-select adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, pp. 460-463, 2011, IEEE, 978-1-4577-1845-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
47 | Yajuan He, Chip-Hong Chang |
A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(1), pp. 336-346, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija |
Delay optimization of carry-skip adders and block carry-lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 10th IEEE Symposium on Computer Arithmetic, ARITH 1991, Grenoble, France, June 26-28, 1991, pp. 154-164, 1991, IEEE, 0-8186-9151-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
44 | Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis |
The circuit design of multiple-valued logic voltage-mode adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 162-165, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Roger Endrigo Carvalho Porto, Luciano Volcan Agostini |
Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 224-229, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Javier D. Bruguera, Tomás Lang |
Multilevel reverse most-significant carry computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 959-962, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Ahmad A. Hiasat |
High-Speed and Reduced-Area Modular Adder Structures for RNS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(1), pp. 84-89, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
modular adder, hardware requirements, VLSI, Computer arithmetic, Residue Number System, time delay, carry-lookahead adder |
32 | Peter Kornerup |
Digit-Set Conversions: Generalizations and Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(5), pp. 622-629, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
conditional sum addition, digit set conversion, multiplier recoding, nonredundant representation, on-the-fly conversion, parallel prefix computation, carry-lookahead techniques, computer arithmetic, digital arithmetic, multiplying circuits, redundant representation |
32 | Stamatis Vassiliadis, James Phillips, Bart Blaner |
Interlock Collapsing ALU's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(7), pp. 825-839, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement |
32 | Barry S. Fagin |
Fast Addition of Large Integers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(9), pp. 1069-1077, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
computation time asymmetry, large integers, massively parallel algorithms, average case behavior, large n-bit additions, multiple bits, parallel algorithms, computational model, digital arithmetic, massively parallel processor, binary addition, carry-lookahead |
32 | Richard P. Brent, H. T. Kung 0001 |
A Regular Layout for Parallel Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(3), pp. 260-264, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
area-time complexity, parallel addition, parallel polynomial evaluation, VLSI, models of computation, circuit design, Addition, combinational logic, prefix computation, carry lookahead |
32 | Daniel E. Atkins, Shauchi Ong |
Time-Component Complexity of Two Approaches to Multioperand Binary Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(12), pp. 918-926, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
time-component complexity, Adder tree, multioperand addition, carry-save adder, carry-lookahead adder, binary addition |
32 | Stephen H. Unger |
Tree Realizations of Iterative Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(4), pp. 365-383, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
conditional sum, flow tables, high speed arithmetic units, iterative circuits, modular circuits, semi-groups, tree circuits, synthesis, combinational circuits, Adders, carry lookahead, binary adders |
32 | Siyi Wang, Anubhab Baksi, Anupam Chattopadhyay |
A Higher Radix Architecture for Quantum Carry-lookahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.02921, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
32 | Bhaskar Gaur, Edgard Muñoz-Coreas, Himanshu Thapliyal |
A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n - 1) Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the Great Lakes Symposium on VLSI 2023, GLSVLSI 2023, Knoxville, TN, USA, June 5-7, 2023, pp. 125-130, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
32 | Francisco Orts, Gloria Ortega López, Ernestas Filatovas, Ester M. Garzón |
Implementation of three efficient 4-digit fault-tolerant quantum carry lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 78(11), pp. 13323-13341, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
32 | Muhammad Ali Akbar, Bo Wang 0012, Amine Bermak |
Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Open J. Circuits Syst. ![In: IEEE Open J. Circuits Syst. 3, pp. 50-58, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
32 | Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus |
Quantum circuit designs of carry lookahead adder optimized for T-count T-depth and qubits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sustain. Comput. Informatics Syst. ![In: Sustain. Comput. Informatics Syst. 29(Part), pp. 100457, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
32 | Haowei Jiang, Feiwei Qin, Jin Cao, Yong Peng 0001, Yanli Shao |
Recurrent Neural Network from Adder's Perspective: Carry-lookahead RNN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2106.12901, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
32 | Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus |
Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2106.04758, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
32 | Haowei Jiang, Feiwei Qin, Jin Cao, Yong Peng 0001, Yanli Shao |
Recurrent neural network from adder's perspective: Carry-lookahead RNN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Networks ![In: Neural Networks 144, pp. 297-306, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
32 | Jaeyoon Park, Youngmin Kim |
Design and Implementation of Ternary Carry Lookahead Adder on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEIC ![In: International Conference on Electronics, Information, and Communication, ICEIC 2021, Jeju, South Korea, January 31 - February 3, 2021, pp. 1-2, 2021, IEEE, 978-1-7281-9161-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
32 | Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus |
T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2004.01826, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
32 | Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus |
Special Session: Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 38th IEEE International Conference on Computer Design, ICCD 2020, Hartford, CT, USA, October 18-21, 2020, pp. 5-8, 2020, IEEE, 978-1-7281-9710-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
32 | Gongzhi Liu, Lijing Zheng, Guangyi Wang, Yiran Shen 0002, Yan Liang 0005 |
A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 43691-43696, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
32 | P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis |
Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1901.09315, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
32 | P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis |
Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1903.09433, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
32 | Torben Ægidius Mogensen |
Reversible In-Place Carry-Lookahead Addition with Few Ancillae. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RC ![In: Reversible Computation - 11th International Conference, RC 2019, Lausanne, Switzerland, June 24-25, 2019, Proceedings, pp. 224-237, 2019, Springer, 978-3-030-21499-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
32 | Nancy S. Soliman, Mohammed E. Fouda, Lobna A. Said, Ahmed H. Madian, Ahmed G. Radwan |
N-digits Ternary Carry Lookahead Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 31st International Conference on Microelectronics, ICM 2019, Cairo, Egypt, December 15-18, 2019, pp. 142-145, 2019, IEEE, 978-1-7281-4058-2. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
32 | Sayantani Roy, Arighna Deb, Debesh K. Das |
Delay Efficient All Optical Carry Lookahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers, pp. 236-244, 2019, Springer, 978-981-32-9766-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
32 | P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis |
Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018, pp. 587-590, 2018, IEEE, 978-1-5386-7392-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
32 | Abdulmajeed Alghamdi, Fayez Gebali |
Performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACRIM ![In: IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM 2015, Victoria, BC, Canada, August 24-26, 2015, pp. 80-83, 2015, IEEE, 978-1-4673-7788-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
32 | Mat Binggeli, Spencer Denton, Naga Spandana Muppaneni, Steve Chiu |
Optimizing carry-lookahead logic through a comparison of PMOS and NMOS block inversions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: IEEE International Conference on Electro/Information Technology, EIT 2015, Dekalb, IL, USA, May 21-23, 2015, pp. 641-646, 2015, IEEE, 978-1-4799-8802-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
32 | Mojtaba Valinataj |
A novel self-checking carry lookahead adder with multiple error detection/correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 38(8), pp. 1072-1081, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
32 | Pratik Dutta, Chandan Bandyopadhyay, Chandan Giri, Hafizur Rahaman 0001 |
Mach-Zehnder Interferometer Based All Optical Reversible Carry-Lookahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014, pp. 412-417, 2014, IEEE Computer Society, 978-1-4799-3763-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
32 | P. Balasubramanian, D. Dhivyaa, J. P. Jayakirthika, P. Kaviyarasi, K. Prasad |
Low power self-timed carry lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 457-460, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | Wesley Chu, Ali I. Unwala, Pohan Wu, Earl E. Swartzlander Jr. |
Implementation of a high speed multiplier using carry lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 2013 Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, November 3-6, 2013, pp. 400-404, 2013, IEEE, 978-1-4799-2390-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | A. H. Shaltoot, Ahmed H. Madian |
Memristor based carry lookahead adder architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012, pp. 298-301, 2012, IEEE, 978-1-4673-2526-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
32 | Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici |
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 1715-1718, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
32 | Radu Zlatanovici, Sean Kao, Borivoje Nikolic |
Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 44(2), pp. 569-583, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
32 | Agung Trisetyarso, Rodney Van Meter |
Circuit Design for A Measurement-Based Quantum Carry-Lookahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/0903.0748, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
32 | Gang-Neng Sung, Chun-Ying Juan, Chua-Chin Wang |
A 32-bit carry lookahead adder design using complementary all-N-transistor logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 706-709, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Ranando King, Hai Jiang 0003 |
CSPA: An Adder Faster Than Carry-Lookahead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2008 International Conference on Computer Design, CDES 2008, Las Vegas, Nevada, USA, July 14-17, 2008, pp. 17-22, 2008, CSREA Press, 1-60132-056-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
32 | Fatemeh Kashfi, Amir Agah, Sied Mehdi Fakhraie, Saeed Safari |
15GHz low-voltage-swing carry-lookahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 4(22), pp. 696-700, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Thomas G. Draper, Samuel A. Kutin, Eric M. Rains, Krysta M. Svore |
A logarithmic-depth quantum carry-lookahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Quantum Inf. Comput. ![In: Quantum Inf. Comput. 6(4), pp. 351-369, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Kuo-Hsing Cheng, Shun-Wen Cheng, Wen-Shiuan Lee |
64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 15(1), pp. 13-28, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Younggap You, Yong-Dae Kim, Jong Hwa Choi |
Dynamic Decimal Adder Circuit Design by using the Carry Lookahead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006, pp. 244-246, 2006, IEEE Computer Society, 1-4244-0185-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Wenjing Rao, Alex Orailoglu, Ramesh Karri |
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 63-68, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Sean Kao, Radu Zlatanovici, Borivoje Nikolic |
A 240ps 64b carry-lookahead adder in 90nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006, pp. 1735-1744, 2006, IEEE, 1-4244-0079-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Ge Yang 0004, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang |
A 32-bit carry lookahead adder using dual-path all-N logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(8), pp. 992-996, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | John T. O'Donnell, Gudula Rünger |
Derivation of a logarithmic time carry lookahead addition circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Funct. Program. ![In: J. Funct. Program. 14(6), pp. 697-713, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas |
Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 181-185, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ECDL, CMOS, adder, digital circuits |
32 | Ge Yang 0004, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang |
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 781-784, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
32 | James Levy, Jabulani Nyathi |
A High Performance, Low Area Overhead Carry Lookahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA/VLSI ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '04 & Proceedings of the International Conference on VLSI, VLSI '04, June 21-24, 2004, Las Vegas, Nevada, USA, pp. 417-426, 2004, CSREA Press, 1-932415-41-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
32 | Radu Zlatanovici, Borivoje Nikolic |
Power-performance optimal 64-bit carry-lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2003 - 29th European Solid-State Circuits Conference, Estoril, Portugal, September 16-18, 2003, pp. 321-324, 2003, IEEE, 0-7803-7995-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Bhushan A. Shinkre, James E. Stine |
A pipelined clock-delayed domino carry-lookahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 171-175, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Kuo-Hsing Cheng, Wen-Shiuan Lee, Yung-Chong Huang |
A 1.2 V 500 MHz 32-bit carry-lookahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 765-768, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Joonho Lim, Dong-Gyu Kim, Soo-Ik Chae |
A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(6), pp. 898-903, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Alessandro De Gloria, Mauro Olivieri |
Statistical Carry Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(3), pp. 340-347, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
32 | June Wang, Zhongde Wang, Graham A. Jullien, William C. Miller |
Area-Time Analysis of Carry Lookahead Adders Using Enhanced Multiple Output Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, pp. 59-62, 1994, IEEE, 0-7803-1916-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
32 | Clark D. Thomborson, Yi Sun |
Optimizing carry lookahead adders for semicustom CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, Kalamazoo, MI, USA, March 5-6, 1993, pp. 119-122, 1993, IEEE, 0-8186-3430-8. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
32 | Thomas W. Lynch, Earl E. Swartzlander Jr. |
A Spanning Tree Carry Lookahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(8), pp. 931-939, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
32 | Tin-Fook Ngai, Mary Jane Irwin, Shishpal Rawat |
Regular Area-Time Efficient Carry-Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 3(1), pp. 92-105, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
32 | Tin-Fook Ngai, Mary Jane Irwin |
Regular, area-time efficient carry-lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 7th IEEE Symposium on Computer Arithmetic, ARITH 1985, Urbana, IL, USA, June 4-6, 1985, pp. 9-15, 1985, IEEE, 0-8186-0632-0. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
29 | Sabyasachi Das, Sunil P. Khatri |
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(3), pp. 326-331, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Yajuan He, Chip-Hong Chang |
A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Ajay Kumar Verma, Paolo Ienne |
Towards the automatic exploration of arithmetic-circuit architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 445-450, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Michael Nicolaidis |
Carry checking/parity prediction adders and ALUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(1), pp. 121-128, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Marius Padure, Sorin Cotofana, Stamatis Vassiliadis |
CMOS Implementation of Generalized Threshold Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN (2) ![In: Artificial Neural Nets Problem Solving Methods, 7th International Work-Conference on Artificial and Natural Neural Networks, IWANN2003, Maó, Menorca, Spain, June 3-6, 2003 Proceedings, Part II, pp. 65-72, 2003, Springer, 3-540-40211-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Oscal T.-C. Chen, Robin R.-B. Sheen, S. Wang |
A low-power adder operating on effective dynamic data ranges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(4), pp. 435-453, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Ravichandran Ramachandran, Shih-Lien Lu |
Efficient arithmetic using self-timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(4), pp. 445-454, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
20 | Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz |
A fault tolerant, area efficient architecture for Shor's factoring algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 383-394, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ion trap, control, quantum computing, layout, cad |