Search results for "carry-lookahead"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
126	Vitit Kantabutra	A Recursive Carry-Lookahead/Carry-Select Hybrid Adder.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	recursive carry-lookahead/carry-select hybrid adder, double-precision mantissas, spanning tree carry lookahead adder, redundant cell adder, Am29050 microprocessor, Manchester carry chains, delays, adders
125	Yu-Ting Pai, Yu-Kumg Chen	The Fastest Carry Lookahead Adder.	DELTA	2004	DBLP DOI BibTeX RDF	central processing unit, integrated circuit, adder, gate delay, carry lookahead adder
104	Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald	Self-Timed Carry-Lookahead Adders.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	delay-insenstive circuits, tree iterative circuits, CMOS, Self-timed circuits, carry-lookahead adders
82	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis	C-Testable modified-Booth multipliers.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model
82	Jin-Fu Li 0001, Jiunn-Der Yu, Yu-Jen Huang	A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
80	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Easily Testable Cellular Carry Lookahead Adders.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model
80	Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka	A fast hybrid carry-lookahead/carry-select adder design.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF	CMOS, domino logic, carry lookahead adder
80	Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija	Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	delay optimisation, block carry-lookahead adders, multidimensional dynamic programming, worst-case carry propagation delays, minimum latency, fanin, dynamic programming, digital arithmetic, adders, gate delays, carry logic, fanout, critical path delay, carry-skip adders
67	Wen-Chang Yeh, Chein-Wei Jen	Generalized Earliest-First Fast Addition Algorithm.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Carry-propagation adder, final adder, conditional-sum, carry-lookahead
67	John P. Fishburn	A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-between.	DAC	1990	DBLP DOI BibTeX RDF
64	Tom Rhyne	Limitations on Carry Lookahead Networks.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	high-speed arithmetic, Binary addition, carry lookahead
63	Hussain Al-Asaad, John P. Hayes, Brian T. Murray	Scalable Test Generators for High-Speed Datapath Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	datapath circuits, scalability, built-in self-test, test generation, on-line testing, carry lookahead
62	P. Balasubramanian 0001, Cuong Dang, Douglas L. Maskell, K. Prasad	Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic.	CoRR	2017	DBLP BibTeX RDF
61	Yijun Liu, Stephen B. Furber	The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics.	PATMOS	2005	DBLP DOI BibTeX RDF
52	Scott Hauck, Matthew M. Hosler, Thomas W. Fry	High-performance carry chains for FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
52	Scott Hauck, Matthew M. Hosler, Thomas W. Fry	High-Performance Carry Chains for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
48	R. D. (Shawn) Blanton, John P. Hayes	Design of a fast, easily testable ALU.	VTS	1996	DBLP DOI BibTeX RDF	ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit
47	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López	Low depth carry lookahead addition using charge recycling threshold logic.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
47	Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang	A 1.25 GHz 32-bit tree-structured carry lookahead adder.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
47	Sae Hwan Kim, Shiu-Kai Chin	Formal Verification of Tree-Structured Carry-Lookahead Adders.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
47	Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho	Delay-Insensitive Carry-Lookahead Adders.	VLSI Design	1997	DBLP DOI BibTeX RDF
47	Shobhit Belwal, Rajat Bhattacharjya, Kaustav Goswami 0002, Dip Sankar Banerjee	ACLA: An Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction.	ISQED	2021	DBLP DOI BibTeX RDF
47	Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, Yasmin Afsharnezhad, Elham Zahraie Salehi	CL-CPA: A hybrid carry-lookahead/carry-propagate adder for low-power or high-performance operation mode.	Integr.	2017	DBLP DOI BibTeX RDF
47	P. Balasubramanian 0001, Cuong Dang, Douglas L. Maskell, K. Prasad	Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis.	CoRR	2017	DBLP BibTeX RDF
47	P. Balasubramanian 0001, Nikos E. Mastorakis	ASIC-based Implementation of Synchronous Section-Carry Based Carry Lookahead Adders.	CoRR	2016	DBLP BibTeX RDF
47	P. Balasubramanian 0001, Nikos E. Mastorakis	Design of Synchronous Section-Carry Based Carry Lookahead Adders with Improved Figure of Merit.	CoRR	2016	DBLP BibTeX RDF
47	Atef Ibrahim, Fayez Gebali	Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders.	Microelectron. J.	2015	DBLP DOI BibTeX RDF
47	P. Balasubramanian 0001, David A. Edwards, William B. Toms	Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic.	J. Circuits Syst. Comput.	2013	DBLP DOI BibTeX RDF
47	Habib Ghasemizadeh Tamar, Akbar Ghasemizadeh Tamar, Khayrollah Hadidi, Abdollah Khoei, Pourya Hoseini	High speed area reduced 64-bit static hybrid carry-lookahead/carry-select adder.	ICECS	2011	DBLP DOI BibTeX RDF
47	Yajuan He, Chip-Hong Chang	A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
47	Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija	Delay optimization of carry-skip adders and block carry-lookahead adders.	IEEE Symposium on Computer Arithmetic	1991	DBLP DOI BibTeX RDF
44	Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis	The circuit design of multiple-valued logic voltage-mode adders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
35	Roger Endrigo Carvalho Porto, Luciano Volcan Agostini	Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation.	DATE	2004	DBLP DOI BibTeX RDF
34	Javier D. Bruguera, Tomás Lang	Multilevel reverse most-significant carry computation.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
32	Ahmad A. Hiasat	High-Speed and Reduced-Area Modular Adder Structures for RNS.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	modular adder, hardware requirements, VLSI, Computer arithmetic, Residue Number System, time delay, carry-lookahead adder
32	Peter Kornerup	Digit-Set Conversions: Generalizations and Application.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	conditional sum addition, digit set conversion, multiplier recoding, nonredundant representation, on-the-fly conversion, parallel prefix computation, carry-lookahead techniques, computer arithmetic, digital arithmetic, multiplying circuits, redundant representation
32	Stamatis Vassiliadis, James Phillips, Bart Blaner	Interlock Collapsing ALU's.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement
32	Barry S. Fagin	Fast Addition of Large Integers.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	computation time asymmetry, large integers, massively parallel algorithms, average case behavior, large n-bit additions, multiple bits, parallel algorithms, computational model, digital arithmetic, massively parallel processor, binary addition, carry-lookahead
32	Richard P. Brent, H. T. Kung 0001	A Regular Layout for Parallel Adders.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	area-time complexity, parallel addition, parallel polynomial evaluation, VLSI, models of computation, circuit design, Addition, combinational logic, prefix computation, carry lookahead
32	Daniel E. Atkins, Shauchi Ong	Time-Component Complexity of Two Approaches to Multioperand Binary Addition.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	time-component complexity, Adder tree, multioperand addition, carry-save adder, carry-lookahead adder, binary addition
32	Stephen H. Unger	Tree Realizations of Iterative Circuits.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	conditional sum, flow tables, high speed arithmetic units, iterative circuits, modular circuits, semi-groups, tree circuits, synthesis, combinational circuits, Adders, carry lookahead, binary adders
32	Siyi Wang, Anubhab Baksi, Anupam Chattopadhyay	A Higher Radix Architecture for Quantum Carry-lookahead Adder.	CoRR	2023	DBLP DOI BibTeX RDF
32	Bhaskar Gaur, Edgard Muñoz-Coreas, Himanshu Thapliyal	A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n - 1) Adder.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
32	Francisco Orts, Gloria Ortega López, Ernestas Filatovas, Ester M. Garzón	Implementation of three efficient 4-digit fault-tolerant quantum carry lookahead adders.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
32	Muhammad Ali Akbar, Bo Wang 0012, Amine Bermak	Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration.	IEEE Open J. Circuits Syst.	2022	DBLP DOI BibTeX RDF
32	Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus	Quantum circuit designs of carry lookahead adder optimized for T-count T-depth and qubits.	Sustain. Comput. Informatics Syst.	2021	DBLP DOI BibTeX RDF
32	Haowei Jiang, Feiwei Qin, Jin Cao, Yong Peng 0001, Yanli Shao	Recurrent Neural Network from Adder's Perspective: Carry-lookahead RNN.	CoRR	2021	DBLP BibTeX RDF
32	Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus	Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing.	CoRR	2021	DBLP BibTeX RDF
32	Haowei Jiang, Feiwei Qin, Jin Cao, Yong Peng 0001, Yanli Shao	Recurrent neural network from adder's perspective: Carry-lookahead RNN.	Neural Networks	2021	DBLP DOI BibTeX RDF
32	Jaeyoon Park, Youngmin Kim	Design and Implementation of Ternary Carry Lookahead Adder on FPGA.	ICEIC	2021	DBLP DOI BibTeX RDF
32	Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus	T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder.	CoRR	2020	DBLP BibTeX RDF
32	Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus	Special Session: Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing.	ICCD	2020	DBLP DOI BibTeX RDF
32	Gongzhi Liu, Lijing Zheng, Guangyi Wang, Yiran Shen 0002, Yan Liang 0005	A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit.	IEEE Access	2019	DBLP DOI BibTeX RDF
32	P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis	Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results.	CoRR	2019	DBLP BibTeX RDF
32	P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis	Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder.	CoRR	2019	DBLP BibTeX RDF
32	Torben Ægidius Mogensen	Reversible In-Place Carry-Lookahead Addition with Few Ancillae.	RC	2019	DBLP DOI BibTeX RDF
32	Nancy S. Soliman, Mohammed E. Fouda, Lobna A. Said, Ahmed H. Madian, Ahmed G. Radwan	N-digits Ternary Carry Lookahead Adder Design.	ICM	2019	DBLP DOI BibTeX RDF
32	Sayantani Roy, Arighna Deb, Debesh K. Das	Delay Efficient All Optical Carry Lookahead Adder.	VDAT	2019	DBLP DOI BibTeX RDF
32	P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis	Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results.	MWSCAS	2018	DBLP DOI BibTeX RDF
32	Abdulmajeed Alghamdi, Fayez Gebali	Performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles.	PACRIM	2015	DBLP DOI BibTeX RDF
32	Mat Binggeli, Spencer Denton, Naga Spandana Muppaneni, Steve Chiu	Optimizing carry-lookahead logic through a comparison of PMOS and NMOS block inversions.	EIT	2015	DBLP DOI BibTeX RDF
32	Mojtaba Valinataj	A novel self-checking carry lookahead adder with multiple error detection/correction.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
32	Pratik Dutta, Chandan Bandyopadhyay, Chandan Giri, Hafizur Rahaman 0001	Mach-Zehnder Interferometer Based All Optical Reversible Carry-Lookahead Adder.	ISVLSI	2014	DBLP DOI BibTeX RDF
32	P. Balasubramanian, D. Dhivyaa, J. P. Jayakirthika, P. Kaviyarasi, K. Prasad	Low power self-timed carry lookahead adders.	MWSCAS	2013	DBLP DOI BibTeX RDF
32	Wesley Chu, Ali I. Unwala, Pohan Wu, Earl E. Swartzlander Jr.	Implementation of a high speed multiplier using carry lookahead adders.	ACSSC	2013	DBLP DOI BibTeX RDF
32	A. H. Shaltoot, Ahmed H. Madian	Memristor based carry lookahead adder architectures.	MWSCAS	2012	DBLP DOI BibTeX RDF
32	Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici	Design aspects of carry lookahead adders with vertically-stacked nanowire transistors.	ISCAS	2010	DBLP DOI BibTeX RDF
32	Radu Zlatanovici, Sean Kao, Borivoje Nikolic	Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
32	Agung Trisetyarso, Rodney Van Meter	Circuit Design for A Measurement-Based Quantum Carry-Lookahead Adder.	CoRR	2009	DBLP BibTeX RDF
32	Gang-Neng Sung, Chun-Ying Juan, Chua-Chin Wang	A 32-bit carry lookahead adder design using complementary all-N-transistor logic.	ICECS	2008	DBLP DOI BibTeX RDF
32	Ranando King, Hai Jiang 0003	CSPA: An Adder Faster Than Carry-Lookahead.	CDES	2008	DBLP BibTeX RDF
32	Fatemeh Kashfi, Amir Agah, Sied Mehdi Fakhraie, Saeed Safari	15GHz low-voltage-swing carry-lookahead adder.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
32	Thomas G. Draper, Samuel A. Kutin, Eric M. Rains, Krysta M. Svore	A logarithmic-depth quantum carry-lookahead adder.	Quantum Inf. Comput.	2006	DBLP DOI BibTeX RDF
32	Kuo-Hsing Cheng, Shun-Wen Cheng, Wen-Shiuan Lee	64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics.	J. Circuits Syst. Comput.	2006	DBLP DOI BibTeX RDF
32	Younggap You, Yong-Dae Kim, Jong Hwa Choi	Dynamic Decimal Adder Circuit Design by using the Carry Lookahead.	DDECS	2006	DBLP DOI BibTeX RDF
32	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.	ETS	2006	DBLP DOI BibTeX RDF
32	Sean Kao, Radu Zlatanovici, Borivoje Nikolic	A 240ps 64b carry-lookahead adder in 90nm CMOS.	ISSCC	2006	DBLP DOI BibTeX RDF
32	Ge Yang 0004, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang	A 32-bit carry lookahead adder using dual-path all-N logic.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
32	John T. O'Donnell, Gudula Rünger	Derivation of a logarithmic time carry lookahead addition circuit.	J. Funct. Program.	2004	DBLP DOI BibTeX RDF
32	Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas	Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic.	SBCCI	2004	DBLP DOI BibTeX RDF	ECDL, CMOS, adder, digital circuits
32	Ge Yang 0004, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang	A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic.	ISCAS (2)	2004	DBLP BibTeX RDF
32	James Levy, Jabulani Nyathi	A High Performance, Low Area Overhead Carry Lookahead Adder.	ESA/VLSI	2004	DBLP BibTeX RDF
32	Radu Zlatanovici, Borivoje Nikolic	Power-performance optimal 64-bit carry-lookahead adders.	ESSCIRC	2003	DBLP DOI BibTeX RDF
32	Bhushan A. Shinkre, James E. Stine	A pipelined clock-delayed domino carry-lookahead adder.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF
32	Kuo-Hsing Cheng, Wen-Shiuan Lee, Yung-Chong Huang	A 1.2 V 500 MHz 32-bit carry-lookahead adder.	ICECS	2001	DBLP DOI BibTeX RDF
32	Joonho Lim, Dong-Gyu Kim, Soo-Ik Chae	A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
32	Alessandro De Gloria, Mauro Olivieri	Statistical Carry Lookahead Adders.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF
32	June Wang, Zhongde Wang, Graham A. Jullien, William C. Miller	Area-Time Analysis of Carry Lookahead Adders Using Enhanced Multiple Output Domino Logic.	ISCAS	1994	DBLP DOI BibTeX RDF
32	Clark D. Thomborson, Yi Sun	Optimizing carry lookahead adders for semicustom CMOS.	Great Lakes Symposium on VLSI	1993	DBLP DOI BibTeX RDF
32	Thomas W. Lynch, Earl E. Swartzlander Jr.	A Spanning Tree Carry Lookahead Adder.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF
32	Tin-Fook Ngai, Mary Jane Irwin, Shishpal Rawat	Regular Area-Time Efficient Carry-Lookahead Adders.	J. Parallel Distributed Comput.	1986	DBLP DOI BibTeX RDF
32	Tin-Fook Ngai, Mary Jane Irwin	Regular, area-time efficient carry-lookahead adders.	IEEE Symposium on Computer Arithmetic	1985	DBLP DOI BibTeX RDF
29	Sabyasachi Das, Sunil P. Khatri	A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
24	Yajuan He, Chip-Hong Chang	A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier.	ISCAS	2006	DBLP DOI BibTeX RDF
24	Ajay Kumar Verma, Paolo Ienne	Towards the automatic exploration of arithmetic-circuit architectures.	DAC	2006	DBLP DOI BibTeX RDF
24	Michael Nicolaidis	Carry checking/parity prediction adders and ALUs.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
24	Marius Padure, Sorin Cotofana, Stamatis Vassiliadis	CMOS Implementation of Generalized Threshold Functions.	IWANN (2)	2003	DBLP DOI BibTeX RDF
24	Oscal T.-C. Chen, Robin R.-B. Sheen, S. Wang	A low-power adder operating on effective dynamic data ranges.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
24	Ravichandran Ramachandran, Shih-Lien Lu	Efficient arithmetic using self-timing.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
20	Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz	A fault tolerant, area efficient architecture for Shor's factoring algorithm.	ISCA	2009	DBLP DOI BibTeX RDF	ion trap, control, quantum computing, layout, cad