Search results for "clock-schedule"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
98	Atsushi Takahashi 0001, Kazunori Inoue, Yoji Kajitani	Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	clock-tree routing, semi-synchronous, deferred-merge-embedding (DME), synchronous, buffer insertion, buffer sizing, clock-schedule
72	Hai Zhou 0001	Clock schedule verification with crosstalk.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	verification, delay, coupling, clock schedule
69	Ivan S. Kourtev, Eby G. Friedman	Clock skew scheduling for improved reliability via quadratic programming.	ICCAD	1999	DBLP DOI BibTeX RDF
63	Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Functional clock schedule optimization.	VLSI Design	1995	DBLP DOI BibTeX RDF	clock schedule optimization, time frames, level-sensitive sequential circuits, scheduling, delays, delays, timing, sequential circuits, flip-flops, clocks, circuit optimisation, latches, false paths
59	Baris Taskin, Ivan S. Kourtev	Delay insertion method in clock skew scheduling.	ISPD	2005	DBLP DOI BibTeX RDF	delay insertion, re-convergent paths, optimization, linear programming, clock skew
39	Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev	Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
39	Christoph Albrecht, Bernhard Korte, Jürgen Schietke, Jens Vygen	Cycle time and slack optimization for VLSI-chips.	ICCAD	1999	DBLP DOI BibTeX RDF
30	Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi 0001	A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
30	Xinjie Wei, Yici Cai, Xianlong Hong	Clock Skew Scheduling Under Process Variations.	ISQED	2006	DBLP DOI BibTeX RDF
26	Vaibhav Nawale, Thomas W. Chen	Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations.	ICCAD	2006	DBLP DOI BibTeX RDF
26	Stephan Held, Bernhard Korte, Jens Maßberg, Matthias Ringe, Jens Vygen	Clock Scheduling and Clocktree Construction for High Performance ASICS.	ICCAD	2003	DBLP DOI BibTeX RDF	ASIC
21	Atsushi Takahashi 0001	Practical Fast Clock-Schedule Design Algorithms.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2006	DBLP DOI BibTeX RDF
21	Ruiming Chen, Hai Zhou 0001	Clock schedule verification under process variations.	ICCAD	2004	DBLP DOI BibTeX RDF
21	Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Graph algorithms for clock schedule optimization.	ICCAD	1992	DBLP DOI BibTeX RDF
17	Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao	Power Supply Noise Suppression via Clock Skew Scheduling.	ISQED	2002	DBLP DOI BibTeX RDF	Skew Scheduling, Power noise, Clock
17	David E. Wallace, Carlo H. Séquin	ATV: An Abstract Timing Verifier.	DAC	1988	DBLP BibTeX RDF
13	Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson	Synchronization of pipelines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
9	Hai Zhou 0001	Timing Verification with Crosstalk for Transparently Latched Circuits.	DATE	2003	DBLP DOI BibTeX RDF