Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
190 | Tao Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer |
Reliability Modeling and Assurance of Clockless Wave Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 442-450, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
147 | Tao Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi |
Fault tolerant clockless wave pipeline design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 350-356, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
clockless wave pipeline, inter-wave fault, intra-wave fault, fault tolerance, reliability |
92 | Arjan Bink, Richard York |
ARM996HS: The First Licensable, Clockless 32-Bit Processor Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(2), pp. 58-68, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
clockless, low EME, TiDE, Haste, VLSI, low power, SoC, asynchronous, processor, circuit design, ARM, AMBA |
92 | Abdelhalim Alsharqawi, Abdel Ejnioui |
Synthesis of Self-Resetting Stage Logic Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 260-262, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
80 | John Teifel, Rajit Manohar |
A High-Speed Clockless Serial Link Transceiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 12-16 May 2003, Vancouver, BC, Canada, pp. 151-163, 2003, IEEE Computer Society, 0-7695-1898-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
80 | Tao Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri |
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 34-, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
73 | Rashad S. Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui |
Synthesis of Pipelined SRSL Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 71-76, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
61 | Ad M. G. Peeters |
Clockless IC design using handshake technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 169, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Abdel Ejnioui, Abdelhalim Alsharqawi |
Self-resetting stage logic pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 174-177, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
clockless, self-resetting, pipeline, asynchronous |
43 | Ming Yin, Maysam Ghovanloo |
A clockless ultra low-noise low-power wireless implantable neural recording system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1756-1759, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen |
A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 641-648, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Abdelhalim Alsharqawi, Abdel Ejnioui |
Clockless Pipelining for Coarse Grain Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 749-753, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | David Geer |
Is It Time for Clockless Chips? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 38(3), pp. 18-21, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Tobias Bjerregaard, Jens Sparsø |
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1226-1231, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Charbel J. Akl, Magdy A. Bayoumi |
Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 385-390, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
circuit family, low-power, high-speed |
37 | Jo C. Ebergen |
Circuits Without Clocks: What Makes Them Tick? ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: Principles of Distributed Systems, 7th International Conference, OPODIS 2003 La Martinique, French West Indies, December 10-13, 2003 Revised Selected Papers, pp. 2, 2003, Springer, 3-540-22667-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Xiudeng Wang, Yinshui Xia, Ge Shi 0001, Zhangming Zhu, Huakang Xia, Yidie Ye, Zhidong Chen, Libo Qian, Lianxi Liu |
A Clockless Synergistic Hybrid Energy Harvesting Technique With Simultaneous Energy Injection and Sampling for Piezoelectric and Photovoltaic Energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(4), pp. 1795-1804, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Mengyu Li, Shuang Song 0003, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan |
A 1.2V 62.2dB SNDR SAR-Assisted Event-Driven Clockless Level-Crossing ADC for Time-Sparse Signal Acquisition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 289-292, 2023, IEEE, 979-8-3503-0420-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Jinbo Chen, Xing Liu, Hui Wu, Fengshi Tian, Wenjun Zou, Mostafa Katebi, Razieh Eskandari, Jie Yang, Mohamad Sawan |
A Clockless Robust Bionic Spike Detector for Implantable Brain-Computer Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BioCAS ![In: IEEE Biomedical Circuits and Systems Conference, BioCAS 2023, Toronto, ON, Canada, October 19-21, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-0026-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | John Marty Emmert, Anvesh Perumalla, Tristan J. Hudson, Luis Concha |
THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(7), pp. 2906-2915, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Takahiro Kawaguchi, Naofumi Takagi |
32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 105-C(6), pp. 245-250, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Yehuda Kra, Adam Teman |
Silicon-Proven Clockless Wave-Propagated Pipelining for High-Throughput, Energy-Efficient Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 1138-1139, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Vivek Mangal, Peter R. Kinget |
Clockless, Continuous-Time Analog Correlator Using Time-Encoded Signal Processing Demonstrating Asynchronous CDMA for Wake-Up Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 55(8), pp. 2069-2081, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | James R. Hoff |
Conflux - An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(2), pp. 503-515, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Ricardo Aquino Guazzelli, Matheus Garay Trindade, Leonel Acunha Guimaraes, Thiago Ferreira de Paiva Leite, Laurent Fesquet, Rodrigo Possamai Bastos |
Trojan Detection Test for Clockless Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 36(1), pp. 23-31, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Daewoong Lee, Dongil Lee, Yong-Hun Kim, Hyun-Kyu Jeon, Byung-Guk Kim, Lee-Sup Kim |
A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(1), pp. 67-71, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Alessia Maria Elgani, Francesco Renzini, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Canegallo, Giulio Ricotti |
A Clockless Temperature-Compensated Nanowatt Analog Front-End for Wake-Up Radios Based on a Band-Pass Envelope Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8), pp. 2612-2624, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Soheil Salehi, Ramtin Zand, Ronald F. DeMara |
Clockless Spin-based Look-Up Tables with Wide Read Margin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1903.00978, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
25 | Sri Harsh Pakala, Punith R. Surkanti, Paul M. Furth |
A Spread-Spectrum Mode Enabled Ripple-Based Buck Converter Using a Clockless Frequency Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 66-II(2), pp. 382-386, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Soheil Salehi, Ramtin Zand, Ronald F. DeMara |
Clockless Spin-based Look-Up Tables with Wide Read Margin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019, pp. 363-366, 2019, ACM, 978-1-4503-6252-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Xuedi Wang, Xueqing Li, Longqiang Lai, Huazhong Yang |
A 16b Clockless Digital-to-Analog Converter with Ultra-Low-Cost Poly Resistors Supporting Wide-Temperature Range from -40°C to 85°C. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019, pp. 267-270, 2019, ACM, 978-1-4503-6252-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Yu Bai 0004, Ronald F. DeMara, Jia Di, Mingjie Lin |
Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 67(5), pp. 631-645, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Marc Renaudin, Aymane Bouzafour, Sylvain Engels, Robin Wilson |
A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 14(3), pp. 404-413, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Michal Maslik, Tor Sverre Lande, Timothy G. Constandinou |
A Clockless Method of Flicker Noise Suppression in Continuous-Time Acquisition of Biosignals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BioCAS ![In: 2018 IEEE Biomedical Circuits and Systems Conference, BioCAS 2018, Cleveland, OH, USA, October 17-19, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-3603-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Luis Oliveira 0002, Luís Almeida 0001, Daniel Mossé |
A Clockless Synchronisation Framework for Cooperating Mobile Robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTAS ![In: IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2018, 11-13 April 2018, Porto, Portugal, pp. 305-315, 2018, IEEE Computer Society, 978-1-5386-5295-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Ziho Shin, Myeong-Hoon Oh, Jeong-Gun Lee, Hag-Young Kim, Young Woo Kim |
Design of a clockless MSP430 core using mixed asynchronous design flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(8), pp. 20170162, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Dominik Rzepka, Dariusz Koscielnik, Marek Miskowicz |
Clockless signal-dependent compressive sensing of multitone signals using time encoding machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EBCCSP ![In: 3rd International Conference on Event-Based Control, Communication and Signal Processing, EBCCSP 2017, Funchal, Portugal, May 24-26, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-0915-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Xiaoyang Zhang, Zhe Zhang 0008, Yongfu Li 0002, Changrong Liu, Yongxin Guo, Yong Lian 0001 |
A 2.89 µW Dry-Electrode Enabled Clockless Wireless ECG SoC for Wearable Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(10), pp. 2287-2298, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Tamer Elsalahati, Ezz I. El-Masry, Dalia A. El-Dib |
High precision clockless ADC using wavelet neural network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 28th International Conference on Microelectronics, ICM 2016, Giza, Egypt, December 17-20, 2016, pp. 365-368, 2016, IEEE, 978-1-5090-5721-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Zhe Zhang 0008, Yongfu Li 0002, Guoxing Wang, Yong Lian 0001 |
A clockless FSK receiver architecture with scalable data rate for epidermal electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BioCAS ![In: IEEE Biomedical Circuits and Systems Conference, BioCAS 2016, Shanghai, China, October 17-19, 2016, pp. 400-403, 2016, IEEE, 978-1-5090-2959-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Yan Liu 0016, João L. Pereira, Timothy G. Constandinou |
Clockless continuous-time neural spike sorting: Method, implementation and evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 538-541, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Xiaolin Xu, Daniel E. Holcomb |
A Clockless Sequential PUF with Autonomous Majority Voting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016, pp. 27-32, 2016, ACM, 978-1-4503-4274-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Xiaoyang Zhang, Zhe Zhang 0008, Yongfu Li 0002, Changrong Liu, Yongxin Guo, Yong Lian 0001 |
A 2.89-μW clockless wireless dry-electrode ECG SoC for wearable sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015, pp. 1-4, 2015, IEEE, 978-1-4673-7191-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet |
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 76(2), pp. 185-194, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Marc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson, Sylvain Engels |
Clockless Design Performance Monitoring for Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 20th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2014, Potsdam, Germany, May 12-14, 2014, pp. 108-109, 2014, IEEE Computer Society, 978-1-4799-3789-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Chris Ceroici, Vincent C. Gaudet |
FPGA implementation of a clockless stochastic LDPC decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: 2014 IEEE Workshop on Signal Processing Systems, SiPS 2014, Belfast, United Kingdom, October 20-22, 2014, pp. 210-214, 2014, IEEE, 978-14799-6588-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Mohammad Alhawari, Michael H. Perrott |
A clockless, multi-stable, CMOS analog circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 1764-1767, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Colin Weltin-Wu, Yannis P. Tsividis |
An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 48(9), pp. 2180-2190, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Roddy C. McLachlan, Alan Gillespie, Michael C. W. Coln, Douglas Chisholm, Denise T. Lee |
A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 48(12), pp. 3028-3037, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Christos Vezyrtzis, Weiwei Jiang 0002, Steven M. Nowick, Yannis P. Tsividis |
A flexible, clockless digital filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference, Bucharest, Romania, September 16-20, 2013, pp. 65-68, 2013, IEEE, 978-1-4799-0643-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Yi Li, Xu Cheng 0002, Yicheng Zhang, Weijing Shi, Jun Han 0003, Xiaoyang Zeng |
A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BioCAS ![In: 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31 - Nov. 2, 2013, pp. 154-157, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Roddy C. McLachlan, Alan Gillespie, Michael C. W. Coln, Douglas Chisholm, Denise T. Lee |
A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013, pp. 278-279, 2013, IEEE, 978-1-4673-4515-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet |
Clockless Stochastic Decoding of Low-Density Parity-Check Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: 2012 IEEE Workshop on Signal Processing Systems, Quebec City, QC, Canada, October 17-19, 2012, pp. 143-148, 2012, IEEE, 978-1-4673-2986-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Julian P. Murphy |
Clockless Physical Unclonable Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TRUST ![In: Trust and Trustworthy Computing - 5th International Conference, TRUST 2012, Vienna, Austria, June 13-15, 2012. Proceedings, pp. 110-121, 2012, Springer, 978-3-642-30920-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Philippe Matherat, Marc-Thierry Jaekel |
Relativistic Causality and Clockless Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 7(4), pp. 20:1-20:19, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Philippe Matherat, Marc-Thierry Jaekel |
Relativistic causality and clockless circuits ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1112.5200, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
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25 | Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu |
Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(8), pp. 1933-1943, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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25 | Venkata Narasimha Manyam, Dhurv Chhetri, J. Jacob Wikner |
Clockless asynchronous delta modulator based ADC for smart dust applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011, pp. 331-336, 2011, IEEE, 978-1-4577-0171-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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25 | Tao Feng, Noh-Jin Park, Minsu Choi, Nohpill Park |
Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 59(7), pp. 1812-1824, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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25 | Ryan D. Jorgenson, Lief Sorensen, Dan Leet, Michael S. Hagedorn, David R. Lamb, Thomas Hal Friddell, Warren P. Snapp |
Ultralow-Power Operation in Subthreshold Regimes Applying Clockless Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 98(2), pp. 299-314, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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25 | Mariya Kurchuk, Yannis P. Tsividis |
Signal-Dependent Variable-Resolution Clockless A/D Conversion With Application to Continuous-Time Digital Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(5), pp. 982-991, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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25 | Hua Wang 0001, Chaoxing Yan, Nan Wu 0002, Dewei Yang, Jingming Kuang 0001 |
Maximum Likelihood Clockless Feedback Phase Recovery for MPSK Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Fall ![In: Proceedings of the 72nd IEEE Vehicular Technology Conference, VTC Fall 2010, 6-9 September 2010, Ottawa, Canada, pp. 1-5, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Sylvain Lippi |
Universal Hard Interaction for Clockless ComputationDem Glücklichen schlägt keine Stunde! ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fundam. Informaticae ![In: Fundam. Informaticae 91(2), pp. 357-394, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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25 | Ming Yin, Maysam Ghovanloo |
A flexible clockless 32-ch simultaneous wireless neural recording system with adjustable resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009, pp. 432-433, 2009, IEEE, 978-1-4244-3458-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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25 | Bob Schell, Yannis P. Tsividis |
A Clockless ADC/DSP/DAC System with Activity-Dependent Power Dissipation and No Aliasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008, pp. 550-551, 2008, IEEE, 978-1-4244-2010-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Martin Simlastík, Viera Stopjaková, Libor Majer, Peter Malík |
Clockless Implementation of LEON2 for Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007, pp. 215-218, 2007, IEEE Computer Society, 1-4244-1161-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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25 | Arjan Bink, Richard York |
ARM996HS™ the first licensable, clockless 32-bit processor core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Chips Symposium ![In: 2006 IEEE Hot Chips 18 Symposium (HCS), Stanford, CA, USA, August 20-22, 2006, pp. 1-28, 2006, IEEE, 978-1-4673-8867-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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25 | Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez |
Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006, pp. 105-108, 2006, IEEE, 1-4244-0075-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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25 | Behnam Analui, Ali Hajimiri |
Instantaneous Clockless Data Recovery and Demultiplexing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 52-II(8), pp. 437-441, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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25 | Laurent Fesquet, Marc Renaudin |
A Programmable Logic Architecture for Prototyping Clockless Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 293-298, 2005, IEEE, 0-7803-9362-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Uri Cummings |
PivotPoint: Clockless Crossbar Switch for High-Performance Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 24(2), pp. 48-59, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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25 | Soha Hassoun, Yong-Bin Kim, Fabrizio Lombardi |
Guest Editors' Introduction: Clockless VLSI Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(6), pp. 5-8, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Suhwan Kim, Conrad H. Ziesler |
A clockless future for systems on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(6), pp. 120-, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
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25 | Richard Sandige, Albert A. Liddicoat, Bryan Mealy |
Modeling, Simulating, and Implementing Clockless Finite State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Modelling, Simulation, and Optimization ![In: Proceedings of the IASTED International Conference on Modelling, Simulation and Optimization - MSO 2003, Banff, Canada, July 2-4, 2003, pp. 19-22, 2003, IASTED/ACTA Press, 0-88986-372-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
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18 | Martin Simlastík, Viera Stopjaková |
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 348-358, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT |
18 | Indranil Saha, Janardan Misra, Suman Roy 0001 |
Timeout and Calendar Based Finite State Modeling and Verification of Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis, 5th International Symposium, ATVA 2007, Tokyo, Japan, October 22-25, 2007, Proceedings, pp. 284-299, 2007, Springer, 978-3-540-75595-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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18 | Davide Pandini |
Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 254, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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18 | Benjamin Vigoda, Justin Dauwels, Matthias Frey, Neil Gershenfeld, Tobias Koch 0001, Hans-Andrea Loeliger, Patrick R. Merkli |
Synchronization of Pseudorandom Signals by Forward-Only Message Passing With Application to Electronic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 52(8), pp. 3843-3852, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin |
State-holding in Look-Up Tables: application to asynchronous logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 12-17, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Song Peng, Rajit Manohar |
Efficient Failure Detection in Pipelined Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 484-493, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | John Teifel, Rajit Manohar |
An Asynchronous Dataflow FPGA Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(11), pp. 1376-1392, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Asynchronous/synchronous operation, reconfigurable hardware, gate arrays, dataflow architectures |
18 | Abdel Ejnioui, Abdelhalim Alsharqawi |
Pipeline Design Based on Self-Resetting Stage Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 254-257, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Abdel Ejnioui, Abdelhalim Alsharqawi |
Pipeline-Level Control of Self-Resetting Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 342-349, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Jo C. Ebergen, Daniel F. Finchelstein, Russell Kao, Jon K. Lexau, David Hopkins 0001 |
A Fast and Energy-Efficient Stack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 7-16, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Ad M. G. Peeters |
Implementation of Handshake Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
25 Years Communicating Sequential Processes ![In: Communicating Sequential Processes: The First 25 Years, Symposium on the Occasion of 25 Years of CSP, London, UK, July 7-8, 2004, Revised Invited Papers, pp. 98-132, 2004, Springer, 3-540-25813-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Satish K. Bandapati, Scott C. Smith, Minsu Choi |
Design and Characterization of Null Convention Self-Timed Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(6), pp. 26-36, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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18 | Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple |
Power Management in the Amulet Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 18(2), pp. 42-52, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|