Search results for "clockless"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
190	Tao Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer	Reliability Modeling and Assurance of Clockless Wave Pipeline.	DFT	2004	DBLP DOI BibTeX RDF
147	Tao Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi	Fault tolerant clockless wave pipeline design.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	clockless wave pipeline, inter-wave fault, intra-wave fault, fault tolerance, reliability
92	Arjan Bink, Richard York	ARM996HS: The First Licensable, Clockless 32-Bit Processor Core.	IEEE Micro	2007	DBLP DOI BibTeX RDF	clockless, low EME, TiDE, Haste, VLSI, low power, SoC, asynchronous, processor, circuit design, ARM, AMBA
92	Abdelhalim Alsharqawi, Abdel Ejnioui	Synthesis of Self-Resetting Stage Logic Pipelines.	ISVLSI	2005	DBLP DOI BibTeX RDF
80	John Teifel, Rajit Manohar	A High-Speed Clockless Serial Link Transceiver.	ASYNC	2003	DBLP DOI BibTeX RDF
80	Tao Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri	Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults.	DFT	2003	DBLP DOI BibTeX RDF
73	Rashad S. Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui	Synthesis of Pipelined SRSL Circuits.	ISVLSI	2006	DBLP DOI BibTeX RDF
61	Ad M. G. Peeters	Clockless IC design using handshake technology.	ISPD	2006	DBLP DOI BibTeX RDF
49	Abdel Ejnioui, Abdelhalim Alsharqawi	Self-resetting stage logic pipelines.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	clockless, self-resetting, pipeline, asynchronous
43	Ming Yin, Maysam Ghovanloo	A clockless ultra low-noise low-power wireless implantable neural recording system.	ISCAS	2008	DBLP DOI BibTeX RDF
43	Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen	A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip.	DSD	2006	DBLP DOI BibTeX RDF
43	Abdelhalim Alsharqawi, Abdel Ejnioui	Clockless Pipelining for Coarse Grain Datapaths.	VLSI Design	2006	DBLP DOI BibTeX RDF
43	David Geer	Is It Time for Clockless Chips?	Computer	2005	DBLP DOI BibTeX RDF
43	Tobias Bjerregaard, Jens Sparsø	A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip.	DATE	2005	DBLP DOI BibTeX RDF
37	Charbel J. Akl, Magdy A. Bayoumi	Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family.	ISQED	2008	DBLP DOI BibTeX RDF	circuit family, low-power, high-speed
37	Jo C. Ebergen	Circuits Without Clocks: What Makes Them Tick?	OPODIS	2003	DBLP DOI BibTeX RDF
25	Xiudeng Wang, Yinshui Xia, Ge Shi 0001, Zhangming Zhu, Huakang Xia, Yidie Ye, Zhidong Chen, Libo Qian, Lianxi Liu	A Clockless Synergistic Hybrid Energy Harvesting Technique With Simultaneous Energy Injection and Sampling for Piezoelectric and Photovoltaic Energy.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
25	Mengyu Li, Shuang Song 0003, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan	A 1.2V 62.2dB SNDR SAR-Assisted Event-Driven Clockless Level-Crossing ADC for Time-Sparse Signal Acquisition.	ESSCIRC	2023	DBLP DOI BibTeX RDF
25	Jinbo Chen, Xing Liu, Hui Wu, Fengshi Tian, Wenjun Zou, Mostafa Katebi, Razieh Eskandari, Jie Yang, Mohamad Sawan	A Clockless Robust Bionic Spike Detector for Implantable Brain-Computer Interfaces.	BioCAS	2023	DBLP DOI BibTeX RDF
25	John Marty Emmert, Anvesh Perumalla, Tristan J. Hudson, Luis Concha	THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
25	Takahiro Kawaguchi, Naofumi Takagi	32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor.	IEICE Trans. Electron.	2022	DBLP DOI BibTeX RDF
25	Yehuda Kra, Adam Teman	Silicon-Proven Clockless Wave-Propagated Pipelining for High-Throughput, Energy-Efficient Processing.	ISCAS	2022	DBLP DOI BibTeX RDF
25	Vivek Mangal, Peter R. Kinget	Clockless, Continuous-Time Analog Correlator Using Time-Encoded Signal Processing Demonstrating Asynchronous CDMA for Wake-Up Receivers.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
25	James R. Hoff	Conflux - An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
25	Ricardo Aquino Guazzelli, Matheus Garay Trindade, Leonel Acunha Guimaraes, Thiago Ferreira de Paiva Leite, Laurent Fesquet, Rodrigo Possamai Bastos	Trojan Detection Test for Clockless Circuits.	J. Electron. Test.	2020	DBLP DOI BibTeX RDF
25	Daewoong Lee, Dongil Lee, Yong-Hun Kim, Hyun-Kyu Jeon, Byung-Guk Kim, Lee-Sup Kim	A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
25	Alessia Maria Elgani, Francesco Renzini, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Canegallo, Giulio Ricotti	A Clockless Temperature-Compensated Nanowatt Analog Front-End for Wake-Up Radios Based on a Band-Pass Envelope Detector.	IEEE Trans. Circuits Syst. I Regul. Pap.	2020	DBLP DOI BibTeX RDF
25	Soheil Salehi, Ramtin Zand, Ronald F. DeMara	Clockless Spin-based Look-Up Tables with Wide Read Margin.	CoRR	2019	DBLP BibTeX RDF
25	Sri Harsh Pakala, Punith R. Surkanti, Paul M. Furth	A Spread-Spectrum Mode Enabled Ripple-Based Buck Converter Using a Clockless Frequency Control.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
25	Soheil Salehi, Ramtin Zand, Ronald F. DeMara	Clockless Spin-based Look-Up Tables with Wide Read Margin.	ACM Great Lakes Symposium on VLSI	2019	DBLP DOI BibTeX RDF
25	Xuedi Wang, Xueqing Li, Longqiang Lai, Huazhong Yang	A 16b Clockless Digital-to-Analog Converter with Ultra-Low-Cost Poly Resistors Supporting Wide-Temperature Range from -40°C to 85°C.	ACM Great Lakes Symposium on VLSI	2019	DBLP DOI BibTeX RDF
25	Yu Bai 0004, Ronald F. DeMara, Jia Di, Mingjie Lin	Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm.	IEEE Trans. Computers	2018	DBLP DOI BibTeX RDF
25	Marc Renaudin, Aymane Bouzafour, Sylvain Engels, Robin Wilson	A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI.	J. Low Power Electron.	2018	DBLP DOI BibTeX RDF
25	Michal Maslik, Tor Sverre Lande, Timothy G. Constandinou	A Clockless Method of Flicker Noise Suppression in Continuous-Time Acquisition of Biosignals.	BioCAS	2018	DBLP DOI BibTeX RDF
25	Luis Oliveira 0002, Luís Almeida 0001, Daniel Mossé	A Clockless Synchronisation Framework for Cooperating Mobile Robots.	RTAS	2018	DBLP DOI BibTeX RDF
25	Ziho Shin, Myeong-Hoon Oh, Jeong-Gun Lee, Hag-Young Kim, Young Woo Kim	Design of a clockless MSP430 core using mixed asynchronous design flow.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
25	Dominik Rzepka, Dariusz Koscielnik, Marek Miskowicz	Clockless signal-dependent compressive sensing of multitone signals using time encoding machine.	EBCCSP	2017	DBLP DOI BibTeX RDF
25	Xiaoyang Zhang, Zhe Zhang 0008, Yongfu Li 0002, Changrong Liu, Yongxin Guo, Yong Lian 0001	A 2.89 µW Dry-Electrode Enabled Clockless Wireless ECG SoC for Wearable Applications.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
25	Tamer Elsalahati, Ezz I. El-Masry, Dalia A. El-Dib	High precision clockless ADC using wavelet neural network.	ICM	2016	DBLP DOI BibTeX RDF
25	Zhe Zhang 0008, Yongfu Li 0002, Guoxing Wang, Yong Lian 0001	A clockless FSK receiver architecture with scalable data rate for epidermal electronics.	BioCAS	2016	DBLP DOI BibTeX RDF
25	Yan Liu 0016, João L. Pereira, Timothy G. Constandinou	Clockless continuous-time neural spike sorting: Method, implementation and evaluation.	ISCAS	2016	DBLP DOI BibTeX RDF
25	Xiaolin Xu, Daniel E. Holcomb	A Clockless Sequential PUF with Autonomous Majority Voting.	ACM Great Lakes Symposium on VLSI	2016	DBLP DOI BibTeX RDF
25	Xiaoyang Zhang, Zhe Zhang 0008, Yongfu Li 0002, Changrong Liu, Yongxin Guo, Yong Lian 0001	A 2.89-μW clockless wireless dry-electrode ECG SoC for wearable sensors.	A-SSCC	2015	DBLP DOI BibTeX RDF
25	Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet	Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model.	J. Signal Process. Syst.	2014	DBLP DOI BibTeX RDF
25	Marc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson, Sylvain Engels	Clockless Design Performance Monitoring for Nanometer Technologies.	ASYNC	2014	DBLP DOI BibTeX RDF
25	Chris Ceroici, Vincent C. Gaudet	FPGA implementation of a clockless stochastic LDPC decoder.	SiPS	2014	DBLP DOI BibTeX RDF
25	Mohammad Alhawari, Michael H. Perrott	A clockless, multi-stable, CMOS analog circuit.	ISCAS	2014	DBLP DOI BibTeX RDF
25	Colin Weltin-Wu, Yannis P. Tsividis	An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
25	Roddy C. McLachlan, Alan Gillespie, Michael C. W. Coln, Douglas Chisholm, Denise T. Lee	A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
25	Christos Vezyrtzis, Weiwei Jiang 0002, Steven M. Nowick, Yannis P. Tsividis	A flexible, clockless digital filter.	ESSCIRC	2013	DBLP DOI BibTeX RDF
25	Yi Li, Xu Cheng 0002, Yicheng Zhang, Weijing Shi, Jun Han 0003, Xiaoyang Zeng	A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs.	BioCAS	2013	DBLP DOI BibTeX RDF
25	Roddy C. McLachlan, Alan Gillespie, Michael C. W. Coln, Douglas Chisholm, Denise T. Lee	A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability.	ISSCC	2013	DBLP DOI BibTeX RDF
25	Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet	Clockless Stochastic Decoding of Low-Density Parity-Check Codes.	SiPS	2012	DBLP DOI BibTeX RDF
25	Julian P. Murphy	Clockless Physical Unclonable Functions.	TRUST	2012	DBLP DOI BibTeX RDF
25	Philippe Matherat, Marc-Thierry Jaekel	Relativistic Causality and Clockless Circuits.	ACM J. Emerg. Technol. Comput. Syst.	2011	DBLP DOI BibTeX RDF
25	Philippe Matherat, Marc-Thierry Jaekel	Relativistic causality and clockless circuits	CoRR	2011	DBLP BibTeX RDF
25	Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu	Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding.	IEEE Trans. Circuits Syst. I Regul. Pap.	2011	DBLP DOI BibTeX RDF
25	Venkata Narasimha Manyam, Dhurv Chhetri, J. Jacob Wikner	Clockless asynchronous delta modulator based ADC for smart dust applications.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
25	Tao Feng, Noh-Jin Park, Minsu Choi, Nohpill Park	Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design.	IEEE Trans. Instrum. Meas.	2010	DBLP DOI BibTeX RDF
25	Ryan D. Jorgenson, Lief Sorensen, Dan Leet, Michael S. Hagedorn, David R. Lamb, Thomas Hal Friddell, Warren P. Snapp	Ultralow-Power Operation in Subthreshold Regimes Applying Clockless Logic.	Proc. IEEE	2010	DBLP DOI BibTeX RDF
25	Mariya Kurchuk, Yannis P. Tsividis	Signal-Dependent Variable-Resolution Clockless A/D Conversion With Application to Continuous-Time Digital Signal Processing.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
25	Hua Wang 0001, Chaoxing Yan, Nan Wu 0002, Dewei Yang, Jingming Kuang 0001	Maximum Likelihood Clockless Feedback Phase Recovery for MPSK Signals.	VTC Fall	2010	DBLP DOI BibTeX RDF
25	Sylvain Lippi	Universal Hard Interaction for Clockless ComputationDem Glücklichen schlägt keine Stunde!	Fundam. Informaticae	2009	DBLP DOI BibTeX RDF
25	Ming Yin, Maysam Ghovanloo	A flexible clockless 32-ch simultaneous wireless neural recording system with adjustable resolution.	ISSCC	2009	DBLP DOI BibTeX RDF
25	Bob Schell, Yannis P. Tsividis	A Clockless ADC/DSP/DAC System with Activity-Dependent Power Dissipation and No Aliasing.	ISSCC	2008	DBLP DOI BibTeX RDF
25	Martin Simlastík, Viera Stopjaková, Libor Majer, Peter Malík	Clockless Implementation of LEON2 for Low-Power Applications.	DDECS	2007	DBLP DOI BibTeX RDF
25	Arjan Bink, Richard York	ARM996HS™ the first licensable, clockless 32-bit processor core.	Hot Chips Symposium	2006	DBLP DOI BibTeX RDF
25	Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez	Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry.	CICC	2006	DBLP DOI BibTeX RDF
25	Behnam Analui, Ali Hajimiri	Instantaneous Clockless Data Recovery and Demultiplexing.	IEEE Trans. Circuits Syst. II Express Briefs	2005	DBLP DOI BibTeX RDF
25	Laurent Fesquet, Marc Renaudin	A Programmable Logic Architecture for Prototyping Clockless Circuits.	FPL	2005	DBLP DOI BibTeX RDF
25	Uri Cummings	PivotPoint: Clockless Crossbar Switch for High-Performance Embedded Systems.	IEEE Micro	2004	DBLP DOI BibTeX RDF
25	Soha Hassoun, Yong-Bin Kim, Fabrizio Lombardi	Guest Editors' Introduction: Clockless VLSI Systems.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
25	Suhwan Kim, Conrad H. Ziesler	A clockless future for systems on chip.	IEEE Des. Test Comput.	2003	DBLP BibTeX RDF
25	Richard Sandige, Albert A. Liddicoat, Bryan Mealy	Modeling, Simulating, and Implementing Clockless Finite State Machines.	Modelling, Simulation, and Optimization	2003	DBLP BibTeX RDF
18	Martin Simlastík, Viera Stopjaková	Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey.	PATMOS	2008	DBLP DOI BibTeX RDF	Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT
18	Indranil Saha, Janardan Misra, Suman Roy 0001	Timeout and Calendar Based Finite State Modeling and Verification of Real-Time Systems.	ATVA	2007	DBLP DOI BibTeX RDF
18	Davide Pandini	Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies.	IOLTS	2007	DBLP DOI BibTeX RDF
18	Benjamin Vigoda, Justin Dauwels, Matthias Frey, Neil Gershenfeld, Tobias Koch 0001, Hans-Andrea Loeliger, Patrick R. Merkli	Synchronization of Pseudorandom Signals by Forward-Only Message Passing With Application to Electronic Circuits.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
18	Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin	State-holding in Look-Up Tables: application to asynchronous logic.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
18	Song Peng, Rajit Manohar	Efficient Failure Detection in Pipelined Asynchronous Circuits.	DFT	2005	DBLP DOI BibTeX RDF
18	John Teifel, Rajit Manohar	An Asynchronous Dataflow FPGA Architecture.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Asynchronous/synchronous operation, reconfigurable hardware, gate arrays, dataflow architectures
18	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline Design Based on Self-Resetting Stage Logic.	ISVLSI	2004	DBLP DOI BibTeX RDF
18	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline-Level Control of Self-Resetting Pipelines.	DSD	2004	DBLP DOI BibTeX RDF
18	Jo C. Ebergen, Daniel F. Finchelstein, Russell Kao, Jon K. Lexau, David Hopkins 0001	A Fast and Energy-Efficient Stack.	ASYNC	2004	DBLP DOI BibTeX RDF
18	Ad M. G. Peeters	Implementation of Handshake Components.	25 Years Communicating Sequential Processes	2004	DBLP DOI BibTeX RDF
18	Satish K. Bandapati, Scott C. Smith, Minsu Choi	Design and Characterization of Null Convention Self-Timed Multipliers.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
18	Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple	Power Management in the Amulet Microprocessors.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF