Search results for "cmos-nano"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
104	Harika Manem, Garrett S. Rose	The effects of logic partitioning in a majority logic based CMOS-NANO FPGA.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cmos-nano, fpga
70	Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang 0003	Design considerations for variation tolerant multilevel CMOS/Nano memristor memory.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	CMOS/nano, memristor, multi level memories
50	Kevin Ryan, Sansiri Tanachutiwat, Wei Wang 0003	3D CMOL Crossnet for Neuromorphic Network Applications.	NanoNet	2008	DBLP DOI BibTeX RDF	CMOS-Nano Hybrid System, CMOL, Crossnet, Neuromorphic Network, 3D IC
48	Mohammad Tehranipoor, Reza M. Rad	Fine-grained island style architecture for molecular electronic devices.	FPGA	2006	DBLP DOI BibTeX RDF
47	Rajat Subhra Chakraborty, Swarup Bhunia	A study of asynchronous design methodology for robust CMOS-nano hybrid system design.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines
31	Matthew M. Ziegler, Mircea R. Stan	A Case for CMOS/nano co-design.	ICCAD	2002	DBLP DOI BibTeX RDF
29	Ming Liu 0022, Haigang Yang, Sansiri Tanachutiwat, Wei Wang 0003	Carbon Nanotube Nanorelays with Pass-Transistor for FPGA Routing Devices.	NanoNet	2009	DBLP DOI BibTeX RDF	carbon nanorelay, nanoelectromechanical switch, CMOS-nano hybrid, FPGA, carbon nanotube
25	Chen Dong 0003, Deming Chen, Sansiri Tanachutiwat, Wei Wang 0003	Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture.	ICCAD	2007	DBLP DOI BibTeX RDF
18	Joan Santamaria, Nestor Cuevas, Luis E. Rueda G., Javier Ardila, Elkim Roa	A Family of Compact Trim-Free CMOS Nano-Ampere Current References.	ISCAS	2019	DBLP DOI BibTeX RDF
18	Ahmed Reda Mohamed, Mingyi Chen, Guoxing Wang	Untrimmed CMOS Nano-Ampere Current Reference with Curvature-Compensation Scheme.	ISCAS	2019	DBLP DOI BibTeX RDF
18	Jeffrey Abbott, Tianyang Ye, Ling Qin, Marsela Jorgolli, Rona Gertner, Donhee Ham, Hongkun Park	CMOS-nano-bio interface array for cardiac and neuro technology.	ISCAS	2017	DBLP DOI BibTeX RDF
18	Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose	Design Considerations for Multilevel CMOS/Nano Memristive Memory.	ACM J. Emerg. Technol. Comput. Syst.	2012	DBLP DOI BibTeX RDF
18	Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose	Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
18	Ahmad Afifi, Ahmad Ayatollahi, Farshid Raissi, Hassan Hajghassem	Efficient Hybrid CMOS-Nano Circuit Design for Spiking Neurons and Memristive Synapses with STDP.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2010	DBLP DOI BibTeX RDF
18	Ahmad Afifi, Ahmad Ayatollahi, Farshid Raissi	STDP implementation using memristive nanodevice in CMOS-Nano neuromorphic networks.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
18	Ahmad Afifi, Ahmad Ayatollahi, Farshid Raissi	Implementation of biologically plausible spiking neural network models on the memristor crossbar-based CMOS/nano circuits.	ECCTD	2009	DBLP DOI BibTeX RDF
18	Ming Liu, Wei Wang 0003	rFGA: CMOS-nano hybrid FPGA using RRAM components.	NANOARCH	2008	DBLP DOI BibTeX RDF
18	Tahir Ghani	Innovations to extend CMOS nano-transistors to the limit.	ISLPED	2008	DBLP DOI BibTeX RDF
18	Harika Manem, Peter C. Paliwoda, Garrett S. Rose	A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	PMLA, FPGA, hybrid
18	Matthew M. Ziegler, Mircea R. Stan	The CMOS/nano interface from a circuits perspective.	ISCAS (4)	2003	DBLP DOI BibTeX RDF