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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 11 occurrences of 10 keywords
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Results
Found 9 publication records. Showing 9 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
64 | Jiyang Kang, Jongbok Lee, Wonyong Sung |
A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 27(3), pp. 297-312, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
code converter, compiler-friendly, performance evaluation, digital signal processor, architecture synthesis |
22 | Norbert A. Pilz, Kenneth Adamson |
Code Optimization Techniques of Data-Intensive Tasks onto Statically Scheduled Architectures: Optimal Performance on the TigerSharc. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARA ![In: Applied Parallel Computing Advanced Scientific Computing, 6th International Conference, PARA 2002, Espoo, Finland, June 15-18, 2002, Proceedings, pp. 172-184, 2002, Springer, 3-540-43786-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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20 | Zhongyi Lin, Evangelos Georganas, John D. Owens |
Towards Flexible and Compiler-Friendly Layer Fusion for CNNs on Multicore CPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2021: Parallel Processing - 27th International Conference on Parallel and Distributed Computing, Lisbon, Portugal, September 1-3, 2021, Proceedings, pp. 232-248, 2021, Springer, 978-3-030-85664-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Emil Matús, Gordon Cichon, Hendrik Seidel, Pablo Robelly, Torsten Limberg, Gerhard P. Fettweis |
A Compiler-friendly and Low-power DSP architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GI Jahrestagung (1) ![In: 35. Jahrestagung der Gesellschaft für Informatik, Informatik LIVE!, INFORMATIK 2005, Bonn, Germany, September 19-22, 2005, Band 1, pp. 459, 2005, GI, 3-88579-396-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
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14 | Michael J. Schulte, John Glossner, Sanjay Jinturkar, Mayan Moudgill, Suman Mamidi, Stamatis Vassiliadis |
A Low-Power Multithreaded Processor for Software Defined Radio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 43(2-3), pp. 143-159, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low power, wireless communication, computer architecture, multithreading, microarchitecture, Software Defined Radio, processor design |
14 | Michael J. Schulte, C. John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis |
A Low-Power Multithreaded Processor for Baseband Communication Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 393-402, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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14 | Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins |
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 61-70, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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10 | Fabio Campi, Paolo Zoffoli, Claudio Mucci, Massimo Bocchi, Antonio Deledda, Mario de Dominicis, Arseni Vitkovski |
A stream register file unit for reconfigurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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10 | Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen |
A unified processor architecture for RISC & VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 50-55, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual-core processor, register organization, variable-length instruction encoding, digital signal processor |
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