Search results for "compiler-friendly"

Found 9 publication records. Showing 9 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
64	Jiyang Kang, Jongbok Lee, Wonyong Sung	A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	code converter, compiler-friendly, performance evaluation, digital signal processor, architecture synthesis
22	Norbert A. Pilz, Kenneth Adamson	Code Optimization Techniques of Data-Intensive Tasks onto Statically Scheduled Architectures: Optimal Performance on the TigerSharc.	PARA	2002	DBLP DOI BibTeX RDF
20	Zhongyi Lin, Evangelos Georganas, John D. Owens	Towards Flexible and Compiler-Friendly Layer Fusion for CNNs on Multicore CPUs.	Euro-Par	2021	DBLP DOI BibTeX RDF
20	Emil Matús, Gordon Cichon, Hendrik Seidel, Pablo Robelly, Torsten Limberg, Gerhard P. Fettweis	A Compiler-friendly and Low-power DSP architecture.	GI Jahrestagung (1)	2005	DBLP BibTeX RDF
14	Michael J. Schulte, John Glossner, Sanjay Jinturkar, Mayan Moudgill, Suman Mamidi, Stamatis Vassiliadis	A Low-Power Multithreaded Processor for Software Defined Radio.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	low power, wireless communication, computer architecture, multithreading, microarchitecture, Software Defined Radio, processor design
14	Michael J. Schulte, C. John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis	A Low-Power Multithreaded Processor for Baseband Communication Systems.	SAMOS	2004	DBLP DOI BibTeX RDF
14	Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins	ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.	FPL	2003	DBLP DOI BibTeX RDF
10	Fabio Campi, Paolo Zoffoli, Claudio Mucci, Massimo Bocchi, Antonio Deledda, Mario de Dominicis, Arseni Vitkovski	A stream register file unit for reconfigurable processors.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen	A unified processor architecture for RISC & VLIW DSP.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	dual-core processor, register organization, variable-length instruction encoding, digital signal processor

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