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Publication years (Num. hits)
2000-2010 (11)
Publication types (Num. hits)
article(1) inproceedings(10)
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Found 11 publication records. Showing 11 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
48Glenn Leary, Krishna Mehta, Karam S. Chatha Performance and resource optimization of NoC router architecture for master and slave IP cores. Search on Bibsonomy CODES+ISSS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FPGA, network-on-chip
42Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems. Search on Bibsonomy Des. Autom. Embed. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
42Amit Goel, William R. Lee Formal verification of an IBM CoreConnect processor local bus arbiter core. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
33Yafang Wang, Cheng Zhang, Yanli Hou, Boning Hu Implementation of Gigabit Ethernet Network Based on SOPC. Search on Bibsonomy APWCS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF FGPA, coreConnect, PLB-Link, VxWorks, SOPC
33Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan A power estimation methodology for systemC transaction level models. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF CoreConnect, systemC, power analysis, transaction level models, PowerPC
24Douglas Densmore, Adam Donlin, Alberto L. Sangiovanni-Vincentelli FPGA architecture characterization for system level performance analysis. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Fabrizio Ferrandi, Giovanna Ferrara, Roberto Palazzo, Vincenzo Rana, Marco D. Santambrogio VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow. Search on Bibsonomy IPDPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Nobuyuki Ohba, Kohji Takano An SoC design methodology using FPGAs and embedded microprocessors. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF mixed-level verification, SoC, ASIC, FPGA prototyping
24Kyeong Keol Ryu, Vincent John Mooney Automated Bus Generation for Multiprocessor SoC Design. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
24Satnam Singh Interface specification for reconfigurable components. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
24Kyeong Keol Ryu, Eung S. Shin, Vincent John Mooney III A Comparison of Five Different Multiprocessor SoC Bus Architectures. Search on Bibsonomy DSD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
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