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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 15 occurrences of 15 keywords
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Results
Found 34 publication records. Showing 34 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
38 | Ruiqin Xiong, Jizheng Xu, Feng Wu 0001, Shipeng Li 0001, Ya-Qin Zhang |
Subband Coupling Aware Rate Allocation for Spatial Scalability in 3-D Wavelet Video Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 17(10), pp. 1311-1324, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Di Wu 0017, Jiang Hu, Rabi N. Mahapatra |
Coupling aware timing optimization and antenna avoidance in layer assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 20-27, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI, interconnect, probabilistic modeling, physical design, crosstalk, design for manufacturability (DFM), antenna effect |
33 | Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas |
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8), pp. 1256-1263, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang 0001 |
Coupling-aware Dummy Metal Insertion for Lithography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 13-18, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
coupling-aware dummy metal insertion, integrated circuits manufacturing technology, resolution enhancement techniques, off-axis illumination, forbidden pitches, printability improvement, invisible dummy metal segments, lithography cost minimization, optimal algorithm, chemical mechanical polish |
32 | Amitava Bhaduri, Ranga Vemuri |
Moment-driven coupling-aware routing methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 390-395, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
coupling-aware, routing, moments |
32 | Di Wu 0017, Jiang Hu, Min Zhao 0001, Rabi N. Mahapatra |
Timing driven track routing considering coupling capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1156-1159, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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30 | Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou 0001 |
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 486-491, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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25 | Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao |
Coupling aware RLC-based clock routings for crosstalk minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Ninglong Lu, Ibrahim N. Hajj |
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 133-138, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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12 | Ruoyan Ma, Jie Tang 0002, Xiuyin Zhang, Kai-Kit Wong, Jonathon A. Chambers |
Energy-Efficiency Optimization for Mutual-Coupling-Aware Wireless Communication System Based on RIS-Enhanced SWIPT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 10(22), pp. 19399-19414, nov15 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Andrea Abrardo, Davide Dardari, Marco Di Renzo, Xuewen Qian |
MIMO Interference Channels Assisted by Reconfigurable Intelligent Surfaces: Mutual Coupling Aware Sum-Rate Optimization Based on a Mutual Impedance Channel Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Wirel. Commun. Lett. ![In: IEEE Wirel. Commun. Lett. 10(12), pp. 2624-2628, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
12 | Gabriele Gradoni, Marco Di Renzo |
End-to-End Mutual Coupling Aware Communication Model for Reconfigurable Intelligent Surfaces: An Electromagnetic-Compliant Approach Based on Mutual Impedances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Wirel. Commun. Lett. ![In: IEEE Wirel. Commun. Lett. 10(5), pp. 938-942, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
12 | Andrea Abrardo, Davide Dardari, Marco Di Renzo, Xuewen Qian |
MIMO Interference Channels Assisted by Reconfigurable Intelligent Surfaces: Mutual Coupling Aware Sum-Rate Optimization Based on a Mutual Impedance Channel Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2102.07155, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
12 | Gabriele Gradoni, Marco Di Renzo |
End-to-End Mutual-Coupling-Aware Communication Model for Reconfigurable Intelligent Surfaces: An Electromagnetic-Compliant Approach Based on Mutual Impedances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2009.02694, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
12 | Jack S.-Y. Lin, Louis Y.-Z. Lin, Ryan H.-M. Huang, Charles H.-P. Wen |
Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the on Great Lakes Symposium on VLSI 2017, Banff, AB, Canada, May 10-12, 2017, pp. 251-256, 2017, ACM, 978-1-4503-4972-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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12 | Hui-Ju Katherine Chiang, Chi-Yuan Liu, Jie-Hong R. Jiang, Yao-Wen Chang |
Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4), pp. 598-610, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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12 | Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao |
Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2), pp. 161-172, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Maria Predari, Aurélien Esnard |
Coupling-aware graph partitioning algorithms: Preliminary study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: 21st International Conference on High Performance Computing, HiPC 2014, Goa, India, December 17-20, 2014, pp. 1-10, 2014, IEEE Computer Society, 978-1-4799-5976-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
12 | Caleb Serafy, Ankur Srivastava 0001 |
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: International Symposium on Physical Design, ISPD'14, Petaluma, CA, USA, March 30 - April 02, 2014, pp. 55-62, 2014, ACM, 978-1-4503-2592-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
12 | Ashkan Eghbal, Pooria M. Yaghini, Siavash S. Yazdi, Nader Bagherzadeh |
TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, pp. 92-97, 2014, IEEE Computer Society, 978-1-4799-6155-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
12 | Chi-Yuan Liu, Hui-Ju Katherine Chiang, Yao-Wen Chang, Jie-Hong R. Jiang |
Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014, pp. 54:1-54:6, 2014, ACM, 978-1-4503-2730-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
12 | Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang |
Thermal coupling aware task migration using neighboring core search for many-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013, pp. 1-4, 2013, IEEE, 978-1-4673-4435-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
12 | Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao |
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013, pp. 6:1-6:6, 2013, ACM, 978-1-4503-2071-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
12 | Debasish Das, Ahmed Shebaita, Hai Zhou 0001, Yehea I. Ismail, Kip Killpack |
FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 19(3), pp. 443-456, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
12 | Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou 0001 |
Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3), pp. 466-478, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
12 | Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou |
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2258-2264, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Amitava Bhaduri, Ranga Vemuri |
Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 922-923, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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12 | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4134-4137, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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12 | Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim |
Coupling-aware high-level interconnect synthesis [IC layout]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1), pp. 157-164, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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12 | Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang |
Minimum delay optimization for domino circuits - a coupling-aware approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(2), pp. 202-213, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Logic synthesis, coupling, domino logic, delay minimization |
12 | Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim |
Coupling-aware high-level interconnect synthesis for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 609-613, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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12 | Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang |
Coupling-aware minimum delay optimization for domino logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 371-374, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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12 | Ninglong Lu, Ibrahim N. Hajj |
A hierarchical based approach for coupling aware delay analysis of combinational logic blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2000 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, Jounieh, Lebanon, December 17-20, 2000, pp. 1012-1015, 2000, IEEE, 0-7803-6542-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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8 | Ke Cao, Jiang Hu, Mosong Cheng |
Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(12), pp. 1332-1340, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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