Search results for "coupling-aware"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
38	Ruiqin Xiong, Jizheng Xu, Feng Wu 0001, Shipeng Li 0001, Ya-Qin Zhang	Subband Coupling Aware Rate Allocation for Spatial Scalability in 3-D Wavelet Video Coding.	IEEE Trans. Circuits Syst. Video Technol.	2007	DBLP DOI BibTeX RDF
38	Di Wu 0017, Jiang Hu, Rabi N. Mahapatra	Coupling aware timing optimization and antenna avoidance in layer assignment.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI, interconnect, probabilistic modeling, physical design, crosstalk, design for manufacturability (DFM), antenna effect
33	Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas	Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
32	Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang 0001	Coupling-aware Dummy Metal Insertion for Lithography.	ASP-DAC	2007	DBLP DOI BibTeX RDF	coupling-aware dummy metal insertion, integrated circuits manufacturing technology, resolution enhancement techniques, off-axis illumination, forbidden pitches, printability improvement, invisible dummy metal segments, lithography cost minimization, optimal algorithm, chemical mechanical polish
32	Amitava Bhaduri, Ranga Vemuri	Moment-driven coupling-aware routing methodology.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	coupling-aware, routing, moments
32	Di Wu 0017, Jiang Hu, Min Zhao 0001, Rabi N. Mahapatra	Timing driven track routing considering coupling capacitance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
30	Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou 0001	Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering.	ASP-DAC	2008	DBLP DOI BibTeX RDF
25	Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao	Coupling aware RLC-based clock routings for crosstalk minimization.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Ninglong Lu, Ibrahim N. Hajj	A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model.	ISQED	2001	DBLP DOI BibTeX RDF
12	Ruoyan Ma, Jie Tang 0002, Xiuyin Zhang, Kai-Kit Wong, Jonathon A. Chambers	Energy-Efficiency Optimization for Mutual-Coupling-Aware Wireless Communication System Based on RIS-Enhanced SWIPT.	IEEE Internet Things J.	2023	DBLP DOI BibTeX RDF
12	Andrea Abrardo, Davide Dardari, Marco Di Renzo, Xuewen Qian	MIMO Interference Channels Assisted by Reconfigurable Intelligent Surfaces: Mutual Coupling Aware Sum-Rate Optimization Based on a Mutual Impedance Channel Model.	IEEE Wirel. Commun. Lett.	2021	DBLP DOI BibTeX RDF
12	Gabriele Gradoni, Marco Di Renzo	End-to-End Mutual Coupling Aware Communication Model for Reconfigurable Intelligent Surfaces: An Electromagnetic-Compliant Approach Based on Mutual Impedances.	IEEE Wirel. Commun. Lett.	2021	DBLP DOI BibTeX RDF
12	Andrea Abrardo, Davide Dardari, Marco Di Renzo, Xuewen Qian	MIMO Interference Channels Assisted by Reconfigurable Intelligent Surfaces: Mutual Coupling Aware Sum-Rate Optimization Based on a Mutual Impedance Channel Model.	CoRR	2021	DBLP BibTeX RDF
12	Gabriele Gradoni, Marco Di Renzo	End-to-End Mutual-Coupling-Aware Communication Model for Reconfigurable Intelligent Surfaces: An Electromagnetic-Compliant Approach Based on Mutual Impedances.	CoRR	2020	DBLP BibTeX RDF
12	Jack S.-Y. Lin, Louis Y.-Z. Lin, Ryan H.-M. Huang, Charles H.-P. Wen	Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax?	ACM Great Lakes Symposium on VLSI	2017	DBLP DOI BibTeX RDF
12	Hui-Ju Katherine Chiang, Chi-Yuan Liu, Jie-Hong R. Jiang, Yao-Wen Chang	Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
12	Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao	Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
12	Maria Predari, Aurélien Esnard	Coupling-aware graph partitioning algorithms: Preliminary study.	HiPC	2014	DBLP DOI BibTeX RDF
12	Caleb Serafy, Ankur Srivastava 0001	Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts.	ISPD	2014	DBLP DOI BibTeX RDF
12	Ashkan Eghbal, Pooria M. Yaghini, Siavash S. Yazdi, Nader Bagherzadeh	TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip.	DFT	2014	DBLP DOI BibTeX RDF
12	Chi-Yuan Liu, Hui-Ju Katherine Chiang, Yao-Wen Chang, Jie-Hong R. Jiang	Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification.	DAC	2014	DBLP DOI BibTeX RDF
12	Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang	Thermal coupling aware task migration using neighboring core search for many-core systems.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
12	Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao	Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits.	DAC	2013	DBLP DOI BibTeX RDF
12	Debasish Das, Ahmed Shebaita, Hai Zhou 0001, Yehea I. Ismail, Kip Killpack	FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
12	Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou 0001	Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
12	Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou	RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
12	Amitava Bhaduri, Ranga Vemuri	Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric.	DATE	2005	DBLP DOI BibTeX RDF
12	Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang	RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
12	Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim	Coupling-aware high-level interconnect synthesis [IC layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
12	Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang	Minimum delay optimization for domino circuits - a coupling-aware approach.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Logic synthesis, coupling, domino logic, delay minimization
12	Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim	Coupling-aware high-level interconnect synthesis for low power.	ICCAD	2002	DBLP DOI BibTeX RDF
12	Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang	Coupling-aware minimum delay optimization for domino logic circuits.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
12	Ninglong Lu, Ibrahim N. Hajj	A hierarchical based approach for coupling aware delay analysis of combinational logic blocks.	ICECS	2000	DBLP DOI BibTeX RDF
8	Ke Cao, Jiang Hu, Mosong Cheng	Wire Sizing and Spacing for Lithographic Printability and Timing Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF