|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 36 occurrences of 31 keywords
|
|
|
Results
Found 19 publication records. Showing 19 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
40 | Jian Zhao, Hossam S. Hassanein, Jieyi Wu, Junzhou Luo |
Congestion-Aware Multicast Routing for Supporting QoS over the Internet. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the Eighth IEEE Symposium on Computers and Communications (ISCC 2003), 30 June - 3 July 2003, Kiris-Kemer, Turkey, pp. 447-452, 2003, IEEE Computer Society, 0-7695-1961-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
cycle breaking, multicast tree construction, Open Shortest Path First (OSPF), Leaky Bucket (LB), Quality of Service (QoS), Multicast routing, network congestion, Weighted Fair Queuing (WFQ) |
40 | Kwang-Ting Cheng |
Partial scan designs without using a separate scan clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 277-282, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock |
34 | Lev B. Levitin, Mark G. Karpovsky, Mehmet Mustafa |
Deadlock prevention by turn prohibition in interconnection networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-7, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Jian Zhao, Hossam S. Hassanein, Jieyi Wu, Junzhou Luo |
CRMA: A Cycle-breaking Multicast Routing Algorithm for Supporting QoS over the Internet. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 36th Hawaii International Conference on System Sciences (HICSS-36 2003), CD-ROM / Abstracts Proceedings, January 6-9, 2003, Big Island, HI, USA, pp. 285, 2003, IEEE Computer Society, 0-7695-1874-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Sujit Dey, Srimat T. Chakradhar |
Design of testable sequential circuits by repositioning flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 105-114, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cycle-breaking, flip-flop minimization, sequential redundancy, design for testability, sequential circuits, retiming, partial scan, strongly connected components, redundant fault |
19 | Brian A. Malloy, Peter J. Clarke, Errol L. Lloyd |
A Parameterized Cost Model to Order Classes for Class-based Testing of C++ Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 14th International Symposium on Software Reliability Engineering (ISSRE 2003), 17-20 November 2003, Denver, CO, USA, pp. 353-364, 2003, IEEE Computer Society, 0-7695-2007-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Thomas Eiter, Markus Hecher, Rafael Kiesel |
Treewidth-Aware Cycle Breaking for Algebraic Answer Set Counting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KR ![In: Proceedings of the 18th International Conference on Principles of Knowledge Representation and Reasoning, KR 2021, Online event, November 3-12, 2021., pp. 269-279, 2021, 978-1-956792-99-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Vladimir Sudakov, Alexey Kurennykh |
Cycle-Breaking Approach to Reduce Inconsistency in Pairwise Comparisons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSOC (1) ![In: Intelligent Algorithms in Software Engineering - Proceedings of the 9th Computer Science On-line Conference 2020, Volume 1, pp. 395-400, 2020, Springer, 978-3-030-51964-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Álvaro Barbero Jiménez, José R. Dorronsoro |
Cycle-breaking acceleration for support vector regression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neurocomputing ![In: Neurocomputing 74(16), pp. 2649-2656, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Álvaro Barbero Jiménez, Jorge López Lázaro, José R. Dorronsoro |
Cycle-breaking acceleration of SVM training. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neurocomputing ![In: Neurocomputing 72(7-9), pp. 1398-1406, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Lev B. Levitin, Mark G. Karpovsky, Mehmet Mustafa, Lev Zakrevski |
A New Algorithm for Finding Minimal Cycle-Breaking Sets of Turns in a Graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Graph Algorithms Appl. ![In: J. Graph Algorithms Appl. 10(2), pp. 387-420, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Francesco De Pellegrini, David Starobinski, Mark G. Karpovsky, Lev B. Levitin |
Scalable Cycle-Breaking Algorithms for Gigabit Ethernet Backbones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: Proceedings IEEE INFOCOM 2004, The 23rd Annual Joint Conference of the IEEE Computer and Communications Societies, Hong Kong, China, March 7-11, 2004, pp. 2175-2184, 2004, IEEE, 0-7803-8355-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Tatiana Orenstein, Zvi Kohavi, Irith Pomeranz |
An optimal algorithm for cycle breaking in directed graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 71-81, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
weighted feedback vertex set, graph partition, partial scan, graph reduction, feedback vertex set |
15 | Ruiming Chen, Hai Zhou 0001 |
Statistical timing verification for transparently latched circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1847-1855, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Benjamin G. Jackson, Srinivas Aluru, Patrick S. Schnable |
Consensus Genetic Maps: A Graph Theoretic Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSB ![In: Fourth International IEEE Computer Society Computational Systems Bioinformatics Conference, CSB 2005, Stanford, CA, USA, August 8-11, 2005, pp. 35-43, 2005, IEEE Computer Society, 0-7695-2344-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Dong Xiang, Janak H. Patel |
Partial Scan Design Based on Circuit State Information and Functional Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(3), pp. 276-287, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Valid state, invalid state, testability improvement potential, conflict, testability measure, partial scan design |
11 | Dong Xiang, Yi Xu |
A Multiple Phase Partial Scan Design Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 17-22, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Kee Sup Kim, Charles R. Kime |
Partial scan flip-flop selection by use of empirical testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 47-59, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
scan flip-flop selection, serial scan, design for testability, testability, partial scan |
11 | Kwang-Ting Cheng |
Transition fault testing for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12), pp. 1971-1983, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #19 of 19 (100 per page; Change: )
|
|