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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 689 occurrences of 454 keywords
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Results
Found 1008 publication records. Showing 1008 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
96 | Mahmood Fazlali, Mohammad K. Fallah, Mahdy Zolghadr, Ali Zakerolhosseini |
A New Datapath Merging Method for Reconfigurable System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 157-168, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Datapath Merging, Maximum Weighted Clique Algorithm, High Level Synthesis, Reconfigurable Computing |
88 | Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger |
A Synthesis System For Bus-Based Wavefront Array Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 274-283, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations |
87 | Terry Tao Ye, Samit Chaudhuri, F. Huang, Hamid Savoj, Giovanni De Micheli |
Physical synthesis for ASIC datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 365-368, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
79 | Mehrdad Reshadi, Daniel Gajski |
A cycle-accurate compilation algorithm for custom pipelined datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 21-26, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
NISC, cycle-accurate compiler, scheduling |
78 | Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis |
Speedups in embedded systems with a high-performance coprocessor datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(3), pp. 35:1-35:22, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
coprocessor datapath, synthesis, kernels, Performance improvements, design flow, chaining |
78 | Andy Gean Ye, Jonathan Rose |
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 3-13, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
datapath regularity, reconfigurable fabric, FPGA architecture, routing architecture, area efficiency |
70 | Sabyasachi Das, Sunil P. Khatri |
An efficient and regular routing methodology for datapath designsusing net regularity extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1), pp. 93-101, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
70 | Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta 0001 |
Extraction of functional regularity in datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9), pp. 1279-1296, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
69 | Saraju P. Mohanty, N. Ranganathan |
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(2), pp. 330-353, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic frequency clocking, low-power datapath synthesis, multiple voltage scheduling, time-constrained scheduling, High-level synthesis, resource-constrained scheduling |
69 | Mark C. Johnson, Kaushik Roy 0001 |
Datapath scheduling with multiple supply voltages and level converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 2(3), pp. 227-248, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
datapath scheduling, level conversion, scheduling, high-level synthesis, low power design, DSP, power optimization, multiple voltage |
69 | Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo |
The design of dynamically reconfigurable datapath coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(2), pp. 361-384, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
coarse-grain reconfigurable fabric, reconfigurable datapath, Loop pipelining, interconnection design, datapath synthesis |
61 | Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström |
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(1), pp. 5-19, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Reconfigurable, Computer architecture, Interconnect, Flexible |
61 | Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström |
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007, pp. 18-25, 2007, IEEE, 1-4244-1058-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
61 | Andy Gean Ye, Jonathan Rose |
Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(5), pp. 462-473, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
61 | Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin |
Speculative software management of datapath-width for energy optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 78-87, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
narrow-width regions, compiler, reconfigurable computing, speculative execution, energy management, clock-gating |
61 | Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano |
Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 38-43, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
high level and architectural synthesis, reconfigurable computing |
61 | Dmitry V. Ponomarev, Gurhan Kucuk, Kanad Ghose |
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(2), pp. 199-213, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
energy-efficient datapath, Superscalar processor, power reduction, dynamic instruction scheduling |
61 | Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
Design for Self-Checking and Self-Timed Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 417-430, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
asynchronous datapath, differential cascode voltage switch logic, Self-checking, dynamic circuits |
61 | Yiorgos Makris, Jamison Collins, Alex Orailoglu |
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(1), pp. 29-42, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
controller-datapath circuit, hierarchical test path, influence tables, transparency |
61 | Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
A Totally Self-Checking Dynamic Asynchronous Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 27-32, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Totally self-checking asynchronous datapath, differential cascade voltage switch logic, divider |
53 | Bita Gorjiara, Daniel D. Gajski |
Custom Processor Design Using NISC: A Case-Study on DCT algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2005, September 22-23, 2005, New York Metropolitan Area, USA, pp. 55-60, 2005, IEEE Computer Society, 0-7803-9347-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
53 | Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski |
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 69-76, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
53 | Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11102-11103, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
53 | Mahadevamurty Nemani, Vivek Tiwari |
Macro-driven circuit design methodology for high-performance datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 661-666, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
53 | Steve C.-Y. Huang, Wayne H. Wolf |
Unifiable scheduling and allocation for minimizing system cycle time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(2), pp. 197-210, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
52 | Magnus Själander, Per Larsson-Edefors, Magnus Björk |
A Flexible Datapath Interconnect for Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 15-20, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Brian G. VanBuren, Muhammad Shaaban |
MicroTiger: a graphical microcode simulator with a reconfigurable datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCSE ![In: Proceedings of the 38th SIGCSE Technical Symposium on Computer Science Education, SIGCSE 2007, Covington, Kentucky, USA, March 7-11, 2007, pp. 283-287, 2007, ACM, 1-59593-361-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
simulator, visualization, architecture, microcode |
52 | Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo |
Efficient datapath merging for partially reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 969-980, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Marcos R. Boschetti, Ivan Saraiva Silva, Sergio Bampi |
A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 242-247, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
52 | Maciej J. Ciesielski, Serkan Askar, Samuel Levitin |
Analytical approach to layout generation of datapath cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1480-1488, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
52 | Leilei Song, Keshab K. Parhi, Ichiro Kuroda, Takao Nishitani |
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 160-172, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
52 | Kyumyung Choi, Steven P. Levitan |
A flexible datapath allocation method for architectural synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 4(4), pp. 376-404, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
allocation and binding, high-level synthesis |
52 | Samuel Norman Hamilton, Alex Orailoglu, Andre Hertwig |
Self Recovering Controller and Datapath Codesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 596-601, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
52 | István Erényi, István Vassányi, T. Nemes, É. Nikodemusz, Z. Katona |
FPGA-based Automated Datapath Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 664-, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
52 | Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori |
Datapath Generator Based on Gate-Level Symbolic Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 388-393, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
52 | Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam |
Automatic multithreaded pipeline synthesis from transactional datapath specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 314-319, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
automatic pipelining, datapath specification, design exploration of x86 processor pipelines, multithreading, hardware synthesis |
52 | Süleyman Sirri Demirsoy, Martin Langhammer |
Cholesky decomposition using fused datapath synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 241-244, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cholesky, fused datapath synthesis, fpga, floating-point |
52 | Koji Ohashi, Mineo Kaneko |
Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 481-484, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
high-level synthesis, asynchronous circuit, datapath, register binding |
52 | Marco Lanuzza, Martin Margala, Pasquale Corsonello |
Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 161-166, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
reconfigurable computing, datapath, processor-in-memory |
52 | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi |
Simultaneous peak and average power minimization during datapath scheduling for DSP processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 215-220, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
average power, datapath scheduling, dynamic frequency clocking, high-level synthesis, peak power, multiple voltages |
52 | Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose |
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 90-101, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
energy-efficient datapath, superscalar processor, power reduction, dynamic instruction scheduling |
52 | Yiorgos Makris, Jamison Collins, Alex Orailoglu |
Fast hierarchical test path construction for DFT-free controller-datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 185-190, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fast hierarchical test path construction, DFT-free controller-datapath circuits, transparency based scheme, locally generated vectors, global design test, influence tables, valid control state sequences, module testing, fault coverage levels, vector counts, logic testing, test generation, automatic test pattern generation, ATPG, computational cost reduction |
52 | Hussain Al-Asaad, John P. Hayes, Brian T. Murray |
Scalable Test Generators for High-Speed Datapath Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 111-125, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
datapath circuits, scalability, built-in self-test, test generation, on-line testing, carry lookahead |
52 | Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. T. Fernandes |
Datapath Design for a VLIW Video Signal Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 24-35, 1997, IEEE Computer Society, 0-8186-7764-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
datapath design, VLIW video signal processor, very long instruction word, high parallelism, high-level language programmability, high-bandwidth interconnect, high-connectivity register files, parameterizable versions, VLSI, video signal processing, VLIW architectures, compiler design |
44 | Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek |
Fast Module Mapping and Placement for Datapaths in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 123-132, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
44 | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi |
ILP models for simultaneous energy and transient power minimization during behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(1), pp. 186-212, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power |
43 | Subi Arumugam, Alin Dobra, Christopher M. Jermaine, Niketan Pansare, Luis Leopoldo Perez |
The DataPath system: a data-centric analytic processing engine for large data warehouses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the ACM SIGMOD International Conference on Management of Data, SIGMOD 2010, Indianapolis, Indiana, USA, June 6-10, 2010, pp. 519-530, 2010, ACM, 978-1-4503-0032-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
algorithms |
43 | Martin Langhammer |
Floating point datapath synthesis for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 355-360, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel |
Formal datapath representation and manipulation for implementing DSP transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 385-390, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
high-level synthesis, streaming, discrete Fourier transform, linear transform |
43 | Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl |
Customizing the Datapath and ISA of Soft VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, pp. 276-290, 2007, Springer, 978-3-540-69337-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy 0001, Swarup Bhunia, Hamid Mahmoodi |
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(9), pp. 1034-1039, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Petros Oikonomakos, Mark Zwolinski |
On the Design of Self-Checking Controllers with Datapath Interactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(11), pp. 1423-1434, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fault tolerance, Reliability, testing, automatic synthesis, error-checking, redundant design |
43 | Andrea Lodi 0002, Luca Ciccarelli, Claudio Mucci, Roberto Giansante, Andrea Cappelli, Mario Toma |
An Embedded Reconfigurable Datapath for SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 17-20 April 2005, Napa, CA, USA, Proceedings, pp. 303-304, 2005, IEEE Computer Society, 0-7695-2445-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 |
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 206-214, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Koji Ohashi, Mineo Kaneko |
Statistical schedule length analysis in asynchronous datapath synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 700-703, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu |
Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 53(2), pp. 269-278, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Jing-Ling Yang, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
A high-efficiency strongly self-checking asynchronous datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10), pp. 1484-1494, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Fang Fang, Jianwen Zhu |
Automatic process migration of datapath hard IP libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 887-892, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Ju-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo |
A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Graphics Hardware ![In: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Symposium on Graphics Hardware 2004, Grenoble, France, August 29-30, 2004, pp. 107-114, 2004, Eurographics Association, 3-905673-15-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Sunwoong Yang, MoonJoon Kim, JaeHeung Park, Hoon Chang |
A Study on Methodology for Enhancing Reliability of Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2004, International Conference, Assisi, Italy, May 14-17, 2004, Proceedings, Part I, pp. 73-80, 2004, Springer, 3-540-22054-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Katarzyna Leijten-Nowak, Jef L. van Meerbergen |
An FPGA architecture with enhanced datapath functionality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 195-204, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
adder inverting property, application-domain tuning, logic block architectures, FPGAs, DSP, symmetry |
43 | Jürgen Becker 0001, Alexander Thomas, Maik Scheer |
Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 237-242, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Mineo Kaneko, Kazuaki Oshio |
Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 645-648, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Alex Talpasanu, G. Milford, K. S. A. Miles, Jeffrey A. Davis |
Computer Educational Datapath (CED): Basic Computer Design for K-12 Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC ![In: 2003 International Symposium on Information Technology (ITCC 2003), 28-30 April 2003, Las Vegas, NV, USA, pp. 86-90, 2003, IEEE Computer Society, 0-7695-1916-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Nagisa Ishiura, Tatsuo Watanabe |
Datapath oriented codesign method of application specific DSPs using retargetable compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 55-58, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu |
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 459-464, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Santanu Dutta, Wayne H. Wolf |
A circuit-driven design methodology for video signal-processing datapath elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(2), pp. 229-240, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
43 | Joan Carletta, Mehrdad Nourani, Christos A. Papachristou |
Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 278-282, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
43 | Leilei Song, Keshab K. Parhi |
Low-energy software Reed-Solomon codecs using specialized finite field datapath and division-free Berlekamp-Massey algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 84-89, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
43 | Gila Kamhi, Osnat Weissberg, Limor Fix |
Automatic Datapath Extraction for Efficient Usage of HDD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 9th International Conference, CAV '97, Haifa, Israel, June 22-25, 1997, Proceedings, pp. 95-106, 1997, Springer, 3-540-63166-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
43 | Steve C.-Y. Huang, Wayne H. Wolf |
Performance-driven synthesis in controller-datapath systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(1), pp. 68-80, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
43 | Tom Marshburn, Ivy Lui, Rick Brown, Dan Cheung, Gary Lum, Peter Cheng |
DATAPATH: a CMOS data path silicon assembler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 722-729, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
43 | Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu |
Collaborative voltage scaling with online STA and variable-latency datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 347-352, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
collaborative voltage scaling, online STA, variable-latency datapath, adaptive voltage scaling |
43 | Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita |
Polynomial datapath optimization using partitioning and compensation heuristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 931-936, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
modular HED, polynomial datapath, high-level synthesis |
43 | Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton |
A synthesizable datapath-oriented embedded FPGA fabric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 33-41, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
embedded block, field programmable gate array, system-on-chip, synthesis, integrated circuit, datapath |
35 | Takeshi Sugawara 0001, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISA ![In: Information Security Applications, 9th International Workshop, WISA 2008, Jeju Island, Korea, September 23-25, 2008, Revised Selected Papers, pp. 28-40, 2008, Springer, 978-3-642-00305-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Hash function, Hardware architecture, Whirlpool, Cryptographic hardware |
35 | Sabyasachi Das, Sunil P. Khatri |
A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 572-579, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha |
Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 504-512, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | William B. Toms, David A. Edwards, Andrew Bardsley |
Synthesising Heterogeneously Encoded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 138-149, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
High-level macro-modeling and estimation techniques for switching activity and power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(4), pp. 538-557, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte |
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(1), pp. 59-76, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
simulation, optimizations, energy models, Energy estimation |
35 | Chung-Yang Huang, Kwang-Ting Cheng |
Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3), pp. 381-391, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
Integrated test of interacting controllers and datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(3), pp. 401-422, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
built-in self-test, register transfer level, synthesis-for-testability |
35 | Chung-Yang Huang, Kwang-Ting Cheng |
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 118-123, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
35 | David Knapp |
An Interactive Tool for Register-level Structure Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 598-601, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
35 | Markus Püschel, Peter A. Milder, James C. Hoe |
Permuting streaming data using RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 56(2), pp. 10:1-10:34, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
data reordering, linear bit mapping, streaming datapath, stride permutation, Permutation, switch, RAM, connection network, matrix transposition |
35 | Yee Jern Chong, Sri Parameswaran |
Rapid application specific floating-point unit generation with bit-alignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 62-67, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bit-alignment, datapath merging, floating-point |
35 | Ki-Bog Kim, Chi-Ho Lin |
An Optimal ILP Model for Delay Time to Minimize Peak Power and Area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 358-362, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
B&B, scheduling, Pipelined, ILP, area, peak-power, datapath |
34 | Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk |
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 7:1-7:25, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Field programmable gate array, system-on-chip, integrated circuit, silicon debug |
34 | Laura Frigerio, Fabio Salice |
A performance-oriented hardware/software partitioning for datapath applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 55-60, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
hardware/software systems, performance oriented patitioning |
34 | Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek |
Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, pp. 296-301, 2008, Springer, 978-3-540-78609-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy 0001, Shay Gueron |
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 273-278, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Vijay Sundaresan, Ranga Vemuri |
A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 323-328, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu |
Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore, pp. 14, 2006, IEEE Computer Society, 0-7695-2532-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Kaijie Wu 0001, Ramesh Karri |
Fault secure datapath synthesis using hybrid time and hardware redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10), pp. 1476-1485, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Jiang Chau Wang, Paulo Sérgio Cardoso, Jose Artur Quilici González, Marius Strum, Ricardo Pires |
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(4), pp. 333-344, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
test library, RTL architecture, pre-computed testability, self-test |
34 | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi |
Peak Power Minimization Through Datapath Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 121-126, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Yee William Li, George Patounakis, Anup P. Jose, Kenneth L. Shepard, Steven M. Nowick |
Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 12-16 May 2003, Vancouver, BC, Canada, pp. 216-226, 2003, IEEE Computer Society, 0-7695-1898-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Kaijie Wu 0001, Ramesh Karri |
Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 902-911, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna |
Datapath Scheduling using Dynamic Frequency Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA, pp. 65-70, 2002, IEEE Computer Society, 0-7695-1486-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
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