Search results for "eembc"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
188	Markus Levy	Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications.	HiPEAC	2005	DBLP DOI BibTeX RDF
51	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.	FPGA	2009	DBLP DOI BibTeX RDF	eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd
40	Jason A. Poovey, Thomas M. Conte, Markus Levy, Shay Gal-On	A Benchmark Characterization of the EEMBC Benchmark Suite.	IEEE Micro	2009	DBLP DOI BibTeX RDF
40	Markus Levy	EEMBC and the Purposes of Embedded Processor Benchmarking.	ISPASS	2005	DBLP DOI BibTeX RDF
37	Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito 0001	On the exploitation of loop-level parallelism in embedded applications.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	multithreading, Multi-cores, vectorization, libraries, programming models, thread-level speculation, parallel loops, system-on-chip (Soc)
37	Md. Mafijul Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois 0001, Per Stenström	Loop-level Speculative Parallelism in Embedded Applications.	ICPP	2007	DBLP DOI BibTeX RDF
37	Thomas M. Conte	Keynote: Insight, Not (Random) Numbers: An Embedded Perspective.	HiPEAC	2007	DBLP DOI BibTeX RDF
37	Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito 0001	Challenges in exploitation of loop parallelism in embedded applications.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multithreading, multi-cores, vectorization, libraries, programming models, thread-level speculation, parallel loops
33	Markus Levy	Evaluating Digital Entertainment System Performance.	Computer	2005	DBLP DOI BibTeX RDF	DENBench suite, digital media benchmarks, digital device performance, EEMBC, microprocessor systems, benchmarks, MPSoCs
18	Tobias J. K. Edler von Koch, Igor Böhm, Björn Franke	Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions.	CGO	2010	DBLP DOI BibTeX RDF	ARCompact, dual instruction set architecture, variable-length instructions, register allocation, code size, instruction selection
18	Daniel Jones 0005, Nigel P. Topham	High Speed CPU Simulation Using LTU Dynamic Binary Translation.	HiPEAC	2009	DBLP DOI BibTeX RDF
18	Jaejin Lee, Junghyun Kim, Choonki Jang, Seungkyun Kim, Bernhard Egger 0002, Kwangsub Kim, Sangyong Han	FaCSim: a fast and cycle-accurate architecture simulator for embedded systems.	LCTES	2008	DBLP DOI BibTeX RDF	virtual prototyping, architecture simulator, full-system simulation, simulator parallelization, cycle-accurate simulation
18	Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan	Scaling Soft Processor Systems.	FCCM	2008	DBLP DOI BibTeX RDF
18	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	VESPA: portable, scalable, and flexible FPGA-based vector processors.	CASES	2008	DBLP DOI BibTeX RDF	SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
18	Ciji Isen, Lizy Kurian John, Jung Pil Choi, Hyo Jung Song	On the representativeness of embedded Java benchmarks.	IISWC	2008	DBLP DOI BibTeX RDF
18	Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, Takeshi Kataoka	A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery.	DSN	2007	DBLP DOI BibTeX RDF
18	Md. Mafijul Islam	On the Limitations of Compilers to Exploit Thread-Level Parallelism in Embedded Applications.	ACIS-ICIS	2007	DBLP DOI BibTeX RDF
18	Ben L. Titzer, Joshua S. Auerbach, David F. Bacon, Jens Palsberg	The ExoVM system for automatic VM and application reduction.	PLDI	2007	DBLP DOI BibTeX RDF	VM design, VM modularity, pre-initialization, static compilation, embedded systems, static analysis, persistence, feature analysis, dead code elimination
18	Doosan Cho, Ilya Issenin, Nikil D. Dutt, Jonghee W. Yoon, Yunheung Paek	Software controlled memory layout reorganization for irregular array access patterns.	CASES	2007	DBLP DOI BibTeX RDF	energy consumption, data layout, scratch pad memory
18	Suman Mamidi, Michael J. Schulte, Daniel Iancu, C. John Glossner	Architecture Support for Reconfigurable Multithreaded Processors in Programmable Communication Systems.	ASAP	2007	DBLP DOI BibTeX RDF
18	Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne	ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
18	Aaron Smith, Jon Gibson, Bertrand A. Maher, Nicholas Nethercote, Bill Yoder, Doug Burger, Kathryn S. McKinley, James H. Burrill	Compiling for EDGE Architectures.	CGO	2006	DBLP DOI BibTeX RDF
18	David Sheldon, Rakesh Kumar 0002, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen	Application-specific customization of parameterized FPGA soft-core processors.	ICCAD	2006	DBLP DOI BibTeX RDF
18	Somayeh Sardashti, Hamid Reza Ghasemi, Omid Fatemi	Muli-Issue Multi-Threaded Stream Processor.	ICME	2006	DBLP DOI BibTeX RDF
18	Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne	ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.	DATE	2005	DBLP DOI BibTeX RDF
18	Amir Hosein Kamalizad, Nozar Tabrizi, Nader Bagherzadeh, Akira Hatanaka	A Programmable DSP Architecture for Wireless Communication Systems.	ASAP	2005	DBLP DOI BibTeX RDF
18	David F. Bacon, Perry Cheng, David Grove	Garbage collection for embedded systems.	EMSOFT	2004	DBLP DOI BibTeX RDF	mark-and-sweep, tracing, fragmentation, compaction
18	Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt	Introduction of local memory elements in instruction set extensions.	DAC	2004	DBLP DOI BibTeX RDF	ad-hoc functional units, genetic algorithm, ASIPs, coprocessors, instruction set extensions, customizable processors
18	Jaegeun Oh, Seon Wook Kim, Chulwoo Kim	OpenMP and Compilation Issue in Embedded Applications.	WOMPAT	2003	DBLP DOI BibTeX RDF
18	Christoforos E. Kozyrakis, David A. Patterson 0001	Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks.	MICRO	2002	DBLP DOI BibTeX RDF
18	Alan Weiss	Benchmarking, Selection and Debugging of Microcontrollers.	ICCD	1999	DBLP DOI BibTeX RDF