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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5 occurrences of 5 keywords
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Results
Found 9 publication records. Showing 9 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
43 | Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar |
Reducing leakage in a high-performance deep-submicron instruction cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(1), pp. 77-89, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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43 | Ke Meng, Russ Joseph |
Process variation aware cache leakage management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 262-267, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gated-VDD, selective cache ways, low power, process variation, leakage, cache management |
42 | Pradeep S. Nair, Savithra Eratne, Eugene John |
Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 972-975, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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32 | Srivathsan Krishnamohan, Nihar R. Mahapatra |
Increasing the energy efficiency of pipelined circuits via slack redistribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 436-441, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
slack passing, time borrowing, low-power design |
31 | Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar |
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 90-95, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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22 | Kiyofumi Tanaka, Takenori Fujita |
Leakage Energy Reduction in Cache Memory by Software Self-invalidation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings, pp. 163-174, 2007, Springer, 978-3-540-74308-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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22 | Mrinmoy Ghosh, Hsien-Hsin S. Lee |
Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 13th International Conference on Parallel and Distributed Systems, ICPADS 2007, Hsinchu, Taiwan, December 5-7, 2007, pp. 1-8, 2007, IEEE Computer Society, 978-1-4244-1889-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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22 | Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar |
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 147-157, 2001, IEEE Computer Society, 0-7695-1019-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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22 | Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, Rae McLellan |
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACS ![In: Power-Aware Computer Systems, First International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 82-96, 2000, Springer, 3-540-42329-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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