Search results for "gated-VDD"

Found 9 publication records. Showing 9 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
43	Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	Reducing leakage in a high-performance deep-submicron instruction cache.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
43	Ke Meng, Russ Joseph	Process variation aware cache leakage management.	ISLPED	2006	DBLP DOI BibTeX RDF	gated-VDD, selective cache ways, low power, process variation, leakage, cache management
42	Pradeep S. Nair, Savithra Eratne, Eugene John	Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm.	APCCAS	2008	DBLP DOI BibTeX RDF
32	Srivathsan Krishnamohan, Nihar R. Mahapatra	Increasing the energy efficiency of pipelined circuits via slack redistribution.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	slack passing, time borrowing, low-power design
31	Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories	ISLPED	2000	DBLP DOI BibTeX RDF
22	Kiyofumi Tanaka, Takenori Fujita	Leakage Energy Reduction in Cache Memory by Software Self-invalidation.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
22	Mrinmoy Ghosh, Hsien-Hsin S. Lee	Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems.	ICPADS	2007	DBLP DOI BibTeX RDF
22	Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches.	HPCA	2001	DBLP DOI BibTeX RDF
22	Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, Rae McLellan	Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power.	PACS	2000	DBLP DOI BibTeX RDF

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