Search results for "gated-ground"

Searching for phrase gated-ground (changed automatically) with no syntactic query expansion in all metadata.

Found 8 publication records. Showing 8 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
134	Amit Agarwal 0001, Hai Li, Kaushik Roy 0001	DRG-cache: a data retention gated-ground cache for low power.	DAC	2002	DBLP DOI BibTeX RDF	gated-ground, low leakage cache, SRAM
35	Zhiyu Liu, Volkan Kursun	Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS.	ISQED	2007	DBLP DOI BibTeX RDF	Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling
35	Amit Agarwal 0001, Kaushik Roy 0001	A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime.	ISLPED	2003	DBLP DOI BibTeX RDF	diode, low leakage cache, SRAM, gate leakage
30	David Hentrich, Erdal Oruklu, Jafar Saniie	Performance evaluation of SRAM cells in 22nm predictive CMOS technology.	EIT	2009	DBLP DOI BibTeX RDF
20	Swarup Bhunia, Hai Li, Kaushik Roy 0001	A High Performance IDDQ Testable Cache for Scaled CMOS Technologies.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
19	Wasim Hussain, Shah M. Jahinuzzaman	A read-decoupled gated-ground SRAM architecture for low-power embedded memories.	Integr.	2012	DBLP DOI BibTeX RDF
19	Shah M. Jahinuzzaman, Jaspal Singh Shah, David J. Rennie, Manoj Sachdev	Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
19	Amit Agarwal 0001, Hai Li, Kaushik Roy 0001	A single-Vt low-leakage gated-ground cache for deep submicron.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF

Displaying result #1 - #8 of 8 (100 per page; Change: )

Maintained by L3S.

Previously maintained by Jörg Diederich.

Based upon DBLP by Michael Ley.

data released under the ODC-BY 1.0 license