Search results for "hypertransport"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
145	Huandong Wang, Dan Tang, Xiang Gao, Yunji Chen	An Enhanced HyperTransport Controller with Cache Coherence Support for Multiple-CMP.	NAS	2009	DBLP DOI BibTeX RDF
137	David Slogsnat, Alexander Giese, Mondrian Nüssle, Ulrich Brüning 0001	An open-source HyperTransport core.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	HTX, HyperTransport, FPGA, prototyping, RTL
118	David Slogsnat, Alexander Giese, Ulrich Brüning 0001	A versatile, low latency HyperTransport core.	FPGA	2007	DBLP DOI BibTeX RDF	HTX, HyperTransport, FPGA, prototyping, RTL
88	Heiner Litz, Holger Fröning, Ulrich Brüning 0001	A HyperTransport 3 Physical Layer Interface for FPGAs.	ARC	2009	DBLP DOI BibTeX RDF
50	Xiaojun Yang, Fei Chen, Hailiang Cheng, Ninghui Sun	A HyperTransport-based personal parallel computer.	CLUSTER	2008	DBLP DOI BibTeX RDF
50	Fei Chen, Hailiang Cheng, Xiaojun Yang, Rui Liu	Design and implementation of an effective HyperTransport core in FPGA.	CLUSTER	2008	DBLP DOI BibTeX RDF
50	David C. Keezer, Dany Minier, Patrice Ducharme	Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	control structure reliability, multi-gigahertz testing, picosecond timing accuracy, jitter-tolerance testing, jitter injection, fault tolerance, testing
50	Ami Castonguay, Yvon Savaria	Architecture of a hypertransport tunnel.	ISCAS	2006	DBLP DOI BibTeX RDF
50	Ami Castonguay, Yvon Savaria	A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemC.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
38	Huandong Wang, Xiang Gao, Yunji Chen, Dan Tang, Weiwu Hu	A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	loongson, multi-fpga, fpga, evaluation, verification, emulation
38	Qiong Li, Guangming Liu, Yufeng Guo, Hengzhu Liu	A New High-Performance Distributed Shared I/O System.	APPT	2003	DBLP DOI BibTeX RDF
31	Alvin Leng Sun Loke, Bruce Andrew Doyle, Sanjeev K. Maheshwari, Dennis Michael Fischette, Charles Lin Wang, Tin Tin Wee, Emerson S. Fang	An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
31	Federico Silla	HyperTransport.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
31	Bruce Andrew Doyle, Alvin Leng Sun Loke, Sanjeev K. Maheshwari, Charles Lin Wang, Dennis Michael Fischette, Jeffrey G. Cooper, Sanjeev K. Aggarwal, Tin Tin Wee, Chad O. Lackey, Harishkumar S. Kedarnath, Michael M. Oshima, Gerry R. Talbot, Emerson S. Fang	Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors.	A-SSCC	2011	DBLP DOI BibTeX RDF
31	José Duato	HyperTransport™ technology tutorial.	Hot Chips Symposium	2009	DBLP DOI BibTeX RDF
31	Heiner Litz, Holger Fröning, Maximilian Thürmer, Ulrich Brüning 0001	An FPGA based verification platform for HyperTransport 3.x.	FPL	2009	DBLP DOI BibTeX RDF
31	Joseph Antony, Pete P. Janes, Alistair P. Rendell	Exploring Thread and Memory Placement on NUMA Architectures: Solaris and Linux, UltraSPARC/FirePlane and Opteron/HyperTransport.	HiPC	2006	DBLP DOI BibTeX RDF
31	Christian Sauer 0001, Matthias Gries, José Ignacio Gómez, Scott J. Weber, Kurt Keutzer	Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express.	PARELEC	2004	DBLP DOI BibTeX RDF
29	Heiner Litz, Maximilian Thürmer, Ulrich Brüning 0001	TCCluster: A Cluster Architecture Utilizing the Processor Host Interface as a Network Interconnect.	CLUSTER	2010	DBLP DOI BibTeX RDF	HyperTransport, AMD, Opteron, interconnect, HPC, Low latency, high bandwidth
29	Mondrian Nüssle, Benjamin Geib, Holger Fröning, Ulrich Brüning 0001	An FPGA-Based Custom High Performance Interconnection Network.	ReConFig	2009	DBLP DOI BibTeX RDF	hypertransport, network, interconnect, switching, crossbar
19	Rainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl	An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems.	SAMOS	2009	DBLP DOI BibTeX RDF
19	Kai Wang, Xiaomin Li, Xuejun An, Ninghui Sun	Gemini NI: An Integration of Two Network Interfaces.	NAS	2009	DBLP DOI BibTeX RDF
19	Panyong Zhang, Can Ma, Jie Ma, Qiang Li, Dan Meng	HPPNET: A novel network for HPC and its implication for communication software.	IPDPS	2008	DBLP DOI BibTeX RDF
19	Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan	ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator.	FCCM	2008	DBLP DOI BibTeX RDF
19	Jason Cong	A new generation of C-base synthesis tool and domain-specific computing.	SoCC	2008	DBLP DOI BibTeX RDF
19	Heiner Litz, Holger Fröning, Mondrian Nüssle, Ulrich Brüning 0001	VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers.	ICPP	2008	DBLP DOI BibTeX RDF
19	Pat Conway, Bill Hughes	The AMD Opteron Northbridge Architecture.	IEEE Micro	2007	DBLP DOI BibTeX RDF	system topology, northbridge, scalability, microarchitecture, point-to-point networking
19	Nathan Woods	Integrating FPGAs in high-performance computing: the architecture and implementation perspective.	FPGA	2007	DBLP DOI BibTeX RDF	compute acceleration, high-performance computinghigh-performance computing, reconfigurable computing, co-processor
19	Fong Pong, Nian-Feng Tzeng, Koray Öner, Chun Ning, Kwong-Tak Chui, Manoj Ekbote, Yanping Lu	Communication performance of a modular high-bandwidth multiprocessor system.	ICPADS	2007	DBLP DOI BibTeX RDF
19	Rajesh Kota, Rich Oehler	Horus: Large-Scale Symmetric Multiprocessing for Opteron Systems.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Computer System Implementation Multiprocessor Systems
19	Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei	A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis
19	Lloyd Dickman, Greg Lindahl, Dave Olson, Jeff Rubin, Jeff Broughton	PathScale InfiniPath: A First Look.	Hot Interconnects	2005	DBLP DOI BibTeX RDF
19	Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway	The AMD Opteron Processor for Multiprocessor Servers.	IEEE Micro	2003	DBLP DOI BibTeX RDF
19	Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov	Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis