Search results for "intra-processor"

Found 12 publication records. Showing 12 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
44	Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin	Adaptive set pinning: managing shared caches in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	inter-processor, intra-processor, set pinning, CMP, shared cache
29	Kevin J. Barker, Kei Davis, Adolfy Hoisie, Darren J. Kerbyson, Michael Lang 0003, Scott Pakin, José Carlos Sancho	Experiences in scaling scientific applications on current-generation quad-core processors.	IPDPS	2008	DBLP DOI BibTeX RDF
26	Guilin Chen, Mahmut T. Kandemir	Optimizing inter-processor data locality on embedded chip multiprocessors.	EMSOFT	2005	DBLP DOI BibTeX RDF	chip multiprocessors, data locality, stencil computation
23	Junjie Wu 0003, Xiaohui Pan, Guanghui Liu, Baida Zhang, Xuejun Yang	Parallel Data Reuse Theory for OpenMP Applications.	SNPD	2009	DBLP DOI BibTeX RDF	Intra-processor, Inter-processor, Parallel, Locality, Reuse, OpenMP
21	Guilin Chen, Mahmut T. Kandemir	An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF
16	Mario Schweigler	A unified model for inter- and intra-processor concurrency.		2006	RDF
16	Vibha A. Dixit-Radiya, Dhabaleswar K. Panda 0001	Clustering and Intra-Processor Scheduling for Explicitly-Parallel Programs on Distributed-Memory Systems.	IPPS	1994	DBLP DOI BibTeX RDF
16	G. D. Nagendra, V. G. Prem Kumar, B. S. Sheshadri Chakravarthy	Simulation bridge: a framework for multi-processor simulation.	CODES	2002	DBLP DOI BibTeX RDF	simulation framework, instruction set simulator, multiprocessor simulation
11	Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya	Scheduler implementation in MP SoC design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
11	Karam S. Chatha, Ranga Vemuri	An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	HW-SW Codesign, HW-SW Partitioning, Scheduling
8	Binu K. Mathew, Al Davis	A loop accelerator for low power embedded VLIW processors.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	embedded systems, low power design, VLIW
8	Stephen C. Hayne, Mark Pendergast	Techniques and experiences with group support system implementation.	CASCON	1994	DBLP BibTeX RDF	software architecture, distributed computing, object oriented technology