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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 17 occurrences of 13 keywords
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Results
Found 8 publication records. Showing 8 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
107 | Carl Ebeling, Brian Lockyear |
On the performance of level-clocked circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 342-357, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits |
92 | Naresh Maheshwari, Sachin S. Sapatnekar |
Optimizing large multiphase level-clocked circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9), pp. 1249-1264, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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80 | Brian Lockyear, Carl Ebeling |
Optimal retiming of level-clocked circuits using symmetric clock schedules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9), pp. 1097-1109, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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60 | Naresh Maheshwari, Sachin S. Sapatnekar |
Efficient Minarea Retiming of Large Level-Clocked Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 840-845, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Level-clocked, Optimization, Synthesis, Retiming, Area |
60 | Naresh Maheshwari, Sachin S. Sapatnekar |
A Practical Algorithm for Retiming Level-Clocked Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 440-445, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
level-clocked, retiming, clock skew, timing optimization |
49 | Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou |
Optimizing two-phase, level-clocked circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 44(1), pp. 148-199, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
clock tuning, level-clocked circuitry, multiphase clocking, timing analysis and optimization, VLSI, retiming |
35 | Soha Hassoun, Christopher Cromer, Eduardo H. Calvillo Gámez |
Static timing analysis for level-clocked circuits in the presence of crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9), pp. 1270-1277, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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23 | Marios C. Papaefthymiou, Keith H. Randall |
TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993., pp. 497-502, 1993, ACM Press, 0-89791-577-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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