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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 56 occurrences of 39 keywords
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Results
Found 29 publication records. Showing 29 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
79 | O. A. Petlin, Stephen B. Furber |
Scan testing of micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 296-303, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines |
59 | O. A. Petlin, Stephen B. Furber |
Built-In Self-Testing of Micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 22-29, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Built-in self-test, Design for test, Asynchronous design, Micropipelines |
53 | Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan |
A New Control Circuit for Asynchronous Micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(9), pp. 992-997, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
zero-overhead, dual-rail coding, Asynchronous design, micropipeline |
53 | Chih-Ming Chang, Shih-Lien Lu |
Design of a static MIMD data flow processor using micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(3), pp. 370-378, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
48 | Rajat Subhra Chakraborty, Swarup Bhunia |
A study of asynchronous design methodology for robust CMOS-nano hybrid system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(3), pp. 12:1-12:22, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines |
48 | Robert B. Reese, Mitchell A. Thornton, Cherrice Traver |
A Coarse-Grain Phased Logic CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(7), pp. 788-799, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asynchronous, pipelined processor, Automatic synthesis, self-timed, micropipelines |
48 | Craig Farnsworth, David A. Edwards, Jianwei Liu, Shiv S. Sikand |
A hybrid asynchronous system design environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 91-98, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
hybrid asynchronous system design environment, hybrid design scheme, asynchronous circuit synthesis, Tangram silicon complier, synchronous design techniques, concurrency, high level synthesis, asynchronous circuits, power reduction, performance gains, micropipelines |
42 | Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein |
Self-Resetting Latches for Asynchronous Micro-Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 986-989, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee |
Energy-efficient and high performance 2-phase asynchronous micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 1188-1191, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
32 | Haider Alrudainy, Andrey Mokhov, Fei Xia, Alex Yakovlev |
Ultra-Low Energy Data Driven Computing Using Asynchronous Micropipelines and Nano-Electro-Mechanical Relays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pp. 158-163, 2017, IEEE Computer Society, 978-1-5090-6762-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
32 | Thomas Polzer, Andreas Steininger |
SET propagation in micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Karlsruhe, Germany, September 9-11, 2013, pp. 126-133, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | Antonio Cerone, George J. Milne |
A Methodology for the Formal Analysis of Asynchronous Micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, Third International Conference, FMCAD 2000, Austin, Texas, USA, November 1-3, 2000, Proceedings, pp. 246-262, 2000, Springer, 3-540-41219-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
32 | Jo C. Ebergen, Scott Fairbanks, Ivan E. Sutherland |
Predicting Performance of Micropipelines Using Charlie Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 238-246, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Stephen B. Furber, Jianwei Liu |
Dynamic logic in four-phase micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), March 18-21, 1996, Aizu-Wakamatsu, Fukushima, Japan, pp. 11-16, 1996, IEEE Computer Society, 0-8186-7298-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
32 | Kees van Berkel 0001, Arjan Bink |
Single-track handshake signaling with application to micropipelines and handshake circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), March 18-21, 1996, Aizu-Wakamatsu, Fukushima, Japan, pp. 122-133, 1996, IEEE Computer Society, 0-8186-7298-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
32 | Volker Schöber, Thomas Kiel |
An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data Convention. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996, pp. 225-231, 1996, IEEE Computer Society, 0-7803-3541-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
32 | Shih-Lien Lu |
Implementation of micropipelines in enable/disable CMOS differential logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(2), pp. 338-341, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
32 | Ajay Khoche, Erik Brunvand |
Testing micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1994, Salt Lake City, UT, USA, November 3-5, 1994, pp. 239-246, 1994, IEEE, 0-8186-6210-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
32 | Ivan E. Sutherland |
Micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 32(6), pp. 720-738, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
27 | Steven M. Nowick, Montek Singh |
High-Performance Asynchronous Pipelines: An Overview. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 28(5), pp. 8-22, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
elastic circuits, latch controllers, pipelines, asynchronous, dynamic logic, design and test, micropipelines |
27 | Recep O. Ozdag, Peter A. Beerel |
High-Speed QDI Asynchronous Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 13-22, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
conditional split, conditional join, QDI, pipelines, asynchronous, dynamic logic, joins, non-linear, fine-grain, micropipelines, forks |
21 | Raghid Shreih, Maitham Shams |
Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 189-194, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
c-element, gasp, low power, pipeline, asynchronous, multi-threshold |
21 | Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou |
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 1904-1921, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Delong Shang, Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Danil Sokolov, Alexandre Yakovlev |
A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 471-480, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Matthew L. King, Kewal K. Saluja |
Testing Micropipelined Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 329-338, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Gregg N. Hoyer, Gin Yee, Carl Sechen |
Locally clocked pipelines and dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(1), pp. 58-62, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Tony Werner, Venkatesh Akella |
An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 140-151, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen |
The Design of an Asynchronous VHDL Synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 44-51, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Synthesis, VHDL, Asynchronous |
21 | Stephen B. Furber, Paul Day |
Four-phase micropipeline latch control circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(2), pp. 247-253, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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