Search results for "multi-cycle"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
50	Kai Yang, Kwang-Ting Cheng	Efficient identification of multi-cycle false path.	ASP-DAC	2006	DBLP DOI BibTeX RDF
47	Gregory Lucas, Chen Dong 0003, Deming Chen	Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.	FPGA	2010	DBLP DOI BibTeX RDF	multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis
44	Hiroyuki Higuchi	An implication-based method to detect multi-cycle paths in large sequential circuits.	DAC	2002	DBLP DOI BibTeX RDF	multi-cycle path, sequential circuits, ATPG, implication
42	Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.	ISLPED	2006	DBLP DOI BibTeX RDF	intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant
41	María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida	Area optimization of multi-cycle operators in high-level synthesis.	DATE	2007	DBLP DOI BibTeX RDF
34	Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu 0002, Chung-Kuan Cheng, Michael D. Hutton	Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.	ASP-DAC	2006	DBLP DOI BibTeX RDF	biclique covering, false subgraphs, multi-cycle subgraphs, static timing analysis, time shifting
33	Jae-sun Seo, Dennis Sylvester, David T. Blaauw, Himanshu Kaul, Ram Krishnamurthy 0001	A robust edge encoding technique for energy-efficient multi-cycle interconnect.	ISLPED	2007	DBLP DOI BibTeX RDF	multi-cycle interconnect, interconnect, encoding, repeaters
31	Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang	Architecture and synthesis for multi-cycle communication.	ISPD	2003	DBLP DOI BibTeX RDF	RDR, multi-cycle communication, scheduling, interconnect, placement, binding, deep sub-micron, timing closure
29	Mary D. Brown, Jared Stark, Yale N. Patt	Select-free instruction scheduling logic.	MICRO	2001	DBLP DOI BibTeX RDF
29	Hiroyuki Higuchi, Yusuke Matsunaga	Enhancing the performance of multi-cycle path analysis in an industrial setting.	ASP-DAC	2004	DBLP DOI BibTeX RDF
25	Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi	High-level synthesis under multi-cycle interconnect delay.	ASP-DAC	2001	DBLP DOI BibTeX RDF
24	Priyank Kalla, Maciej J. Ciesielski	Testability of Sequential Circuits with Multi-Cycle False Path.	VTS	1997	DBLP DOI BibTeX RDF
23	Mary D. Brown, Yale N. Patt	Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files.	HPCA	2002	DBLP DOI BibTeX RDF	redundant binary, limited bypass, pipelined register file, signed digit
23	Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty	Untestable Multi-Cycle Path Delay Faults in Industrial Designs.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
21	Quang Dinh, Deming Chen, Martin D. F. Wong	Efficient ASIP design for configurable processors with fine-grained resource sharing.	FPGA	2008	DBLP DOI BibTeX RDF	multi-cycle IO, compilation, ASIP, resource sharing, configurable processor
20	Laura Pozzi, Paolo Ienne	Exploiting pipelining to relax register-file port constraints of instruction-set extensions.	CASES	2005	DBLP DOI BibTeX RDF	automatic instruction-set extension, constrained scheduling, embedded customised architectures, multi-cycle register access, input/output
19	Daniel Citron, Dror G. Feitelson, Larry Rudolph	Accelerating Multi-Media Processing by Implementing Memoing in Multiplication and Division Units.	ASPLOS	1998	DBLP DOI BibTeX RDF
19	Md. Abdur Razzaque, Md. Mamun-Or-Rashid, Choong Seon Hong	MC2DR: Multi-cycle Deadlock Detection and Recovery Algorithm for Distributed Systems.	HPCC	2007	DBLP DOI BibTeX RDF
19	Arun Krishnamachary, Jacob A. Abraham	Effects of Multi-cycle Sensitization on Delay Tests.	VLSI Design	2003	DBLP DOI BibTeX RDF
19	Lei Cheng 0001, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig	Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.	ICCAD	2007	DBLP DOI BibTeX RDF
19	Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang	Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication.	ICCAD	2003	DBLP DOI BibTeX RDF
17	Ahmad Ahmadi, Reza Faghih Mirzaee	MIPS-Core Application Specific Instruction-Set Processor for IDEA Cryptography - Comparison between Single-Cycle and Multi-Cycle Architectures.	CoRR	2019	DBLP BibTeX RDF
17	David J. Greaves	Further sub-cycle and multi-cycle schedulling support for Bluespec Verilog.	MEMOCODE	2019	DBLP DOI BibTeX RDF
17	Sun Qiang	A peak power optimization scheduling algorithm for single cycle operations and multi-cycle operations.	ASICON	2015	DBLP DOI BibTeX RDF
17	Irith Pomeranz	On the use of multi-cycle tests for storage of two-cycle broadside tests.	VTS	2014	DBLP DOI BibTeX RDF
15	Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida	Arrival time aware scheduling to minimize clock cycle length.	ASP-DAC	2005	DBLP DOI BibTeX RDF
15	Yi-Wei Ci, Zhan Zhang, De-Cheng Zuo, Zhibo Wu, Xiao-Zong Yang	Communication-Based Prevention of Non-P-Pattern.	SRDS	2009	DBLP DOI BibTeX RDF	multi-cycle checkpointing, fault-tolerance, checkpoint
15	Jason Cong, Yiping Fan, Zhiru Zhang	Architecture-level synthesis for automatic interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding
13	Robert D. Mullins, Andrew West, Simon W. Moore	The design and implementation of a low-latency on-chip network.	ASP-DAC	2006	DBLP DOI BibTeX RDF
12	Qiaoyan Yu, Paul Ampadu	Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment.	DFT	2008	DBLP DOI BibTeX RDF
12	Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida	Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis.	DATE	2005	DBLP DOI BibTeX RDF
12	Ilhyun Kim, Mikko H. Lipasti	Macro-op Scheduling: Relaxing Scheduling Loop Constraints.	MICRO	2003	DBLP DOI BibTeX RDF
12	Ewa Z. Bem, Luke Petelczyc	MiniMIPS: a simulation project for the computer architecture laboratory.	SIGCSE	2003	DBLP DOI BibTeX RDF	simulation in lab environments, computer architecture
11	Zhen Wang, Chunming Ye, Jianquan Guo	Robust optimization of multi-objective multi-cycle remanufacturing supply chain network considering incentive compatibility theory under improved algorithm.	Comput. Ind. Eng.	2024	DBLP DOI BibTeX RDF
11	Xiaofeng Xu, Wenzhi Liu, Mingyue Jiang, Ziru Lin	A multi-cycle and multi-echelon location-routing problem for integrated reverse logistics.	Ind. Manag. Data Syst.	2022	DBLP DOI BibTeX RDF
11	Vicky H. Mak-Hau	A polyhedral study of the cardinality constrained multi-cycle and multi-chain problem on directed graphs.	Comput. Oper. Res.	2018	DBLP DOI BibTeX RDF
11	Anirban Sengupta, Saumya Bhadauria	Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computing.	Adv. Eng. Softw.	2015	DBLP DOI BibTeX RDF
11	Run Yu, PingSun Leung	Optimal harvesting strategies for a multi-cycle and multi-pond shrimp operation: A practical network model.	Math. Comput. Simul.	2005	DBLP DOI BibTeX RDF
10	Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar	Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	Performance evaluation, VLIW, ASIP, Clustered VLIW processors
10	Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty	Path Delay Fault Simulation on Large Industrial Designs.	VTS	2006	DBLP DOI BibTeX RDF
10	Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar	Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.	DATE	2005	DBLP DOI BibTeX RDF
10	Hossein Asadi 0001, Mehdi Baradaran Tahoori	Soft Error Modeling and Protection for Sequential Elements.	DFT	2005	DBLP DOI BibTeX RDF
10	Takafumi Takatsuka, Jun Ogi, Yasuji Ikeda, Kazuki Hizu, Yutaka Inaoka, Shunsuke Sakama, Iori Watanabe, Tatsuya Ishikawa, Shohei Shimada, Junki Suzuki, Hidenori Maeda, Kenji Toshima, Yusuke Nonaka, Akifumi Yamamura, Hideki Ozawa, Fumihiko Koga, Yusuke Oike	A 3.36-μm-Pitch SPAD Photon-Counting Image Sensor Using a Clustered Multi-Cycle Clocked Recharging Technique With an Intermediate Most-Significant-Bit Readout.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
10	Elahe Baratalipour, Arezoo Kamran	SAMA: Self-adjusting multi-cycle approximate adder.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
10	Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima	Test Point Insertion for Multi-Cycle Power-On Self-Test.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
10	Yihua Guo, Li Kang, Renjun Jia, Ting Wang	Multi-cycle Deep Recurrent Learning for Power Consumption Time Series Prediction.	ICCEIC	2023	DBLP DOI BibTeX RDF
10	Libo Wang, Yuhan Liu	Multi-Cycle Emergency Material Dispatch Considering the Impact of Psychological Anxiety Under Public Health Emergencies.	ICNC-FSKD	2023	DBLP DOI BibTeX RDF
10	Takafumi Takatsuka, Jun Ogi, Yasuji Ikeda, Kazuki Hizu, Yutaka Inaoka, Shunsuke Sakama, Iori Watanabe, T. Ishikawa, Shohei Shimada, Junki Suzuki, Hidenori Maeda, Kenji Toshima, Yusuke Nonaka, Akifumi Yamamura, Hideki Ozawa, Fumihiko Koga, Yusuke Oike	A 3.36 µm-pitch SPAD photon-counting image sensor using clustered multi-cycle clocked recharging technique with intermediate most-significant-bit readout.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
10	Zhonghui Li, Panida Chamchang, Lili Niu, Jiangtao Mo	A multi-cycle inventory control model for deteriorating items with partial backlogging under trade credit.	Frontiers Appl. Math. Stat.	2022	DBLP DOI BibTeX RDF
10	Yanxia Liu, Anni Chen, Hongyu Shi, Sijuan Huang, Wanjia Zheng, Zhiqiang Liu, Qin Zhang 0013, Xin Yang	CT synthesis from MRI using multi-cycle GAN for head-and-neck radiation therapy.	Comput. Medical Imaging Graph.	2021	DBLP DOI BibTeX RDF
10	Xiaowei Xu 0004, Jiawei Zhang, Jinglan Liu, Yukun Ding, Tianchen Wang, Hailong Qiu, Haiyun Yuan, Jian Zhuang, Wen Xie, Yuhao Dong, Qianjun Jia, Meiping Huang, Yiyu Shi 0001	Multi-Cycle-Consistent Adversarial Networks for Edge Denoising of Computed Tomography Images.	ACM J. Emerg. Technol. Comput. Syst.	2021	DBLP DOI BibTeX RDF
10	Xiaowei Xu 0004, Jiawei Zhang, Jinglan Liu, Yukun Ding, Tianchen Wang, Hailong Qiu, Haiyun Yuan, Jian Zhuang, Wen Xie, Yuhao Dong, Qianjun Jia, Meiping Huang, Yiyu Shi 0001	Multi-Cycle-Consistent Adversarial Networks for Edge Denoising of Computed Tomography Images.	CoRR	2021	DBLP BibTeX RDF
10	Peter Toth, Hiroki Ishikuro	An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept.	ASP-DAC	2021	DBLP DOI BibTeX RDF
10	Edward Lam 0001, Vicky H. Mak-Hau	Branch-and-cut-and-price for the cardinality-constrained multi-cycle problem in kidney exchange.	Comput. Oper. Res.	2020	DBLP DOI BibTeX RDF
10	Carla Negri Lintzmayer, Flávio Keidi Miyazawa, Phablo F. S. Moura, Eduardo C. Xavier	Randomized approximation scheme for Steiner Multi Cycle in the Euclidean plane.	Theor. Comput. Sci.	2020	DBLP DOI BibTeX RDF
10	Jinglan Liu, Yukun Ding, Jinjun Xiong, Qianjun Jia, Meiping Huang, Jian Zhuang, Bike Xie, Chun-Chen Liu, Yiyu Shi 0001	Multi-Cycle-Consistent Adversarial Networks for CT Image Denoising.	CoRR	2020	DBLP BibTeX RDF
10	Xiang Xu, Megha Nawhal, Greg Mori, Manolis Savva	MCMI: Multi-Cycle Image Translation with Mutual Information Constraints.	CoRR	2020	DBLP BibTeX RDF
10	Andrea Tani, Francesco Chiti, Romano Fantacci, Dania Marabissi	Multi-cycle spectrum sensing for OFDM signals under cyclic frequency offsets in cognitive vehicular networks.	IET Commun.	2020	DBLP DOI BibTeX RDF
10	Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima	FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST.	IEICE Trans. Inf. Syst.	2020	DBLP DOI BibTeX RDF
10	Jinglan Liu, Yukun Ding, Jinjun Xiong, Qianjun Jia, Meiping Huang, Jian Zhuang, Bike Xie, Chun-Chen Liu, Yiyu Shi 0001	Multi-Cycle-Consistent Adversarial Networks for CT Image Denoising.	ISBI	2020	DBLP DOI BibTeX RDF
10	Benjamin Sturm, Ali Sunyaev	Design Principles for Systematic Search Systems: A Holistic Synthesis of a Rigorous Multi-cycle Design Science Research Journey.	Bus. Inf. Syst. Eng.	2019	DBLP DOI BibTeX RDF
10	Sae Kyu Lee, Paul N. Whatmough, David Brooks 0001, Gu-Yeon Wei	A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
10	Carla Negri Lintzmayer, Flávio Keidi Miyazawa, Phablo F. S. Moura, Eduardo C. Xavier	Quasilinear Approximation Scheme for Steiner Multi Cycle in the Euclidean plane.	LAGOS	2019	DBLP DOI BibTeX RDF
10	Stefano Proto, Francesco Ventura, Daniele Apiletti, Tania Cerquitelli, Elena Baralis, Enrico Macii, Alberto Macii	PREMISES, a Scalable Data-Driven Service to Predict Alarms in Slowly-Degrading Multi-Cycle Industrial Processes.	BigData Congress	2019	DBLP DOI BibTeX RDF
10	Helge Spieker, Arnaud Gotlieb, Morten Mossige	Rotational Diversity in Multi-Cycle Assignment Problems.	AAAI	2019	DBLP DOI BibTeX RDF
10	Xing Liu 0002, Linghao Fu, Wenbi Rao, Xiongmin Lin, Mingxi Liao, Bing Shi	Multi-Cycle CPU Design With FPGA for Teaching of Computer Organization Principle.	ICCSE	2019	DBLP DOI BibTeX RDF
10	Mohammed T. Lazim, Mohammed Baniyounis, Samer Z. A. Salah	Harmonics generation Due to Multi-Cycle Auto Reclosing on HV Transmission Lines.	SSD	2019	DBLP DOI BibTeX RDF
10	Helge Spieker, Arnaud Gotlieb, Morten Mossige	Rotational Diversity in Multi-Cycle Assignment Problems.	CoRR	2018	DBLP BibTeX RDF
10	Wonki Lee, Seulgee Kim, DaeEun Kim	Individual Biometric Identification Using Multi-Cycle Electrocardiographic Waveform Patterns.	Sensors	2018	DBLP DOI BibTeX RDF
10	Hesam Sadeghi Gougheri, Mehdi Kiani	A Multi-Cycle Switching Technique for Efficient Ultrasonic Wireless Power Delivery.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
10	Vinicius N. G. Pereira, Mário César San Felice, Pedro Henrique Del Bianco Hokama, Eduardo C. Xavier	The Steiner Multi Cycle Problem with Applications to a Collaborative Truckload Problem.	SEA	2018	DBLP DOI BibTeX RDF
10	Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara	On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST.	ATS	2018	DBLP DOI BibTeX RDF
10	Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima	Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST.	ATS	2018	DBLP DOI BibTeX RDF
10	Sae Kyu Lee, Paul N. Whatmough, Niamh Mulholland, Patrick Hansen, David Brooks 0001, Gu-Yeon Wei	A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET.	ESSCIRC	2018	DBLP DOI BibTeX RDF
10	Valentino Meacci, Enrico Boni, Alessandro Dallai, Alessandro Ramalli, Monica Scaringella, Francesco Guidi, Dario Russo, Stefano Ricci	FPGA-Based Multi Cycle Parallel Architecture for Real-Time Processing in Ultrasound Applications.	ApplePies	2018	DBLP DOI BibTeX RDF
10	Agoritsa Gogoulou, Maria Grigoriadou	Engaging Postgraduate Students in a Wiki-Based Multi-cycle Peer Assessment Activity.	TECH-EDU	2018	DBLP DOI BibTeX RDF
10	Gokul Subramanian Ravi, Mikko H. Lipasti	Timing Speculation in Multi-Cycle Data Paths.	IEEE Comput. Archit. Lett.	2017	DBLP DOI BibTeX RDF
10	Chiapin Wang, Chi-Ming Li, Kuo-Chang Ting	Energy-efficient and QoS-aware discontinuous reception using a multi-cycle mechanism in 3GPP LTE/LTE-advanced.	Telecommun. Syst.	2017	DBLP DOI BibTeX RDF
10	Lennart Tautz, Markus Hüllebrand, Michael Steinmetz, Dirk Voit, Jens Frahm, Anja Hennemuth	Exploration of Interventricular Septum Motion in Multi-Cycle Cardiac MRI.	VCBM	2017	DBLP DOI BibTeX RDF
10	Teodora Chitiboi, Rebecca Ramb, Li Feng, Eve Piekarski, Lennart Tautz, Anja Hennemuth, Leon Axel	Multi-cycle Reconstruction of Cardiac MRI for the Analysis of Inter-ventricular Septum Motion During Free Breathing.	FIMH	2017	DBLP DOI BibTeX RDF
10	Yasser M. H. Abdelhamed, Abu B. Sesay	Multi-cycle cyclostaionary spectrum sensing using canonical correlation analysis.	CCECE	2017	DBLP DOI BibTeX RDF
10	A. H. M. Kamal, Mohammad Mahfuzul Islam	Boosting up the data hiding rate through multi cycle embedment process.	J. Vis. Commun. Image Represent.	2016	DBLP DOI BibTeX RDF
10	Deepak Kachave, Anirban Sengupta	Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
10	Hesam Sadeghi Gougheri, Mehdi Kiani	Current-Based Resonant Power Delivery With Multi-Cycle Switching for Extended-Range Inductive Power Transmission.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
10	Anirban Sengupta, Deepak Kachave	Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis.	ISVLSI	2016	DBLP DOI BibTeX RDF
10	Cemil Cem Gürsoy, Abdullah Yildiz, Sezer Gören 0001	On optimization of multi-cycle tests for test quality and application time.	EWDTS	2016	DBLP DOI BibTeX RDF
10	Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima	Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation.	ATS	2016	DBLP DOI BibTeX RDF
10	Ting He 0002, Yangyang Zhao, Tianyang Li, Dianhui Chu	Research on Quantity-Discount Contract Based Two-Stage Supply Chain Coordination in the Environment of Discrete Multi-cycle Demand.	ICSS	2016	DBLP DOI BibTeX RDF
10	Anirban Sengupta, Saumya Bhadauria	Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis.	Expert Syst. Appl.	2015	DBLP DOI BibTeX RDF
10	Diego González 0002, Guillermo Botella, Carlos García 0001, Anke Meyer-Bäse, Uwe Meyer-Bäse, Manuel Prieto-Matías	Customized Nios II multi-cycle instructions to accelerate block-matching techniques.	Real-Time Image and Video Processing	2015	DBLP DOI BibTeX RDF
10	Nilesh Goel, Tejas Naphade, Souvik Mahapatra	Combined trap generation and transient trap occupancy model for time evolution of NBTI during DC multi-cycle and AC stress.	IRPS	2015	DBLP DOI BibTeX RDF
10	Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue	Designing area-efficient controllers for multi-cycle transient fault tolerant systems.	ETS	2015	DBLP DOI BibTeX RDF
10	Byunghun Lee, Pyungwoo Yeon, Maysam Ghovanloo	A multi-cycle Q-modulation technique for wirelessly-powered biomedical implants.	BioCAS	2015	DBLP DOI BibTeX RDF
10	Anirban Sengupta, Reza Sedaghat	Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget.	CCECE	2015	DBLP DOI BibTeX RDF
10	Dominik Erb, Karsten Scheibler, Matthias Sauer 0002, Sudhakar M. Reddy, Bernd Becker 0001	Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects.	VTS	2015	DBLP DOI BibTeX RDF
10	Hong-Sen Yan, Tian-Hua Jiang, Wen-Wu Shi, Shan Li	An iterative learning method for multi-cycle flexible production/inventory control under random demands.	J. Intell. Fuzzy Syst.	2014	DBLP DOI BibTeX RDF
10	Irith Pomeranz	Multi-cycle broadside tests with runs of constant primary input vectors.	IET Comput. Digit. Tech.	2014	DBLP DOI BibTeX RDF
10	Irith Pomeranz	Design-for-testability for multi-cycle broadside tests by holding of state variables.	ACM Trans. Design Autom. Electr. Syst.	2014	DBLP DOI BibTeX RDF
10	Michal Karczmarek, Arvind, Muralidaran Vijayaraghavan	A new synthesis procedure for atomic rules containing multi-cycle function blocks.	MEMOCODE	2014	DBLP DOI BibTeX RDF
10	Teodora Chitiboi, Anja Hennemuth, Lennart Tautz, Markus Hüllebrand, Jens Frahm, Lars Linsen, Horst K. Hahn	Context-based segmentation and analysis of multi-cycle real-time cardiac MRI.	ISBI	2014	DBLP DOI BibTeX RDF