Search results for "multiplierless"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
97	Somchart Chokchaitam, Masahiro Iwahashi	A New Optimum-Word-Length-Assignment (OWLA) Multiplierless Integer DCT for Lossless/Lossy Image Coding and Its Performance Evaluation.	ACIVS	2007	DBLP DOI BibTeX RDF
81	Benjamin W. Wah, Zhe Wu 0002	Discrete Lagrangian Methods for Designing Multiplierless Two-Channel PR-LP Filter Banks.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
66	Juha Yli-Kaakinen, Tapio Saramäki	Design and implementation of multiplierless adjustable fractional-delay all-pass filters.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
66	Mrinmoy Bhattacharya, Tapio Saramäki	Fourth-order structures for multiplierless realizations of bandpass and bandstop digital filters transformed from all-pole lowpass filters.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
66	Kun-Wah Yip, Yik-Chung Wu, Tung-Sang Ng	A new multiplierless correlator for timing synchronization in IEEE 802.11a WLANs.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
50	Lijie Liu, Trac D. Tran	Rate-Distortion Analysis of Multiplierless Lifting-based IDCT Approximations.	CISS	2007	DBLP DOI BibTeX RDF
50	Qiu-Zhong Wu, Yi-He Sun	An Integrated CAD Tool for ASIC Implementation of Multiplierless FIR Filters with Common Sub-expression Elimination Optimization.	ESTIMedia	2005	DBLP DOI BibTeX RDF
50	Yongtao Wang, Kaushik Roy 0001	A novel low-complexity method for parallel multiplierless implementation of digital FIR filters.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
50	Myung Hoon Sunwoo, Seong Keun Oh	A Multiplierless 2-D Convolver Chip for Real-Time Image Processing.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	image processing, VLSI design, VLSI architecture, convolution, multiplier, digital filter
50	Markus Püschel, Adam C. Zelinski, James C. Hoe	Custom-optimized multiplierless implementations of DSP algorithms.	ICCAD	2004	DBLP DOI BibTeX RDF
50	Kamakshi Sivaramakrishnan, Ivan R. Linscott, G. Leonard Tyler	Design of multiplierless programmable linear phase narrowband-bandpass FIR filters.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
50	R. Thamvichai, Tamal Bose, Miloje S. Radenkovic	Multiplierless predictor for DPCM of images.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
50	Mrinmoy Bhattacharya, Tapio Saramäki	Some observations on multiplierless implementation of linear phase FIR filters.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
50	Benjamin W. Wah, Yi Shang, Zhe Wu 0002	Discrete Lagrangian Method for Optimizing the Design of Multiplierless QMF Filter Banks.	ASAP	1997	DBLP DOI BibTeX RDF
50	Ali N. Akansu	Multiplierless PR quadrature mirror filters for subband image coding.	IEEE Trans. Image Process.	1996	DBLP DOI BibTeX RDF
47	Ben I. Hounsell, Tughrul Arslan, Robert Thomson 0003	Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform.	Soft Comput.	2004	DBLP DOI BibTeX RDF	Robust hardware, Finite impulse response filters, Genetic algorithms, Fault tolerant, Programmable logic arrays, PLAs, FIR filters, Evolvable hardware
47	Khurram Muhammad, Kaushik Roy 0001	A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
47	Ben I. Hounsell, Tughrul Arslan	Evolutionary Design And Adaptation Of Digital Filters Within An Embedded Fault Tolerant Hardware Platform .	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
47	Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin	Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters.	PDCAT	2006	DBLP DOI BibTeX RDF	DWT/IDWT, image coding/decoding system, 4-tap Daubechies filters, multiplierless, low-power, JPEG-2000
47	HyungJun Kim	Image Compression Using Biorthogonal Wavelet Transforms with Multiplierless 2-D Filter Mask Operation.	ICIP (1)	1997	DBLP DOI BibTeX RDF	biorthogonal wavelet transforms, dyadic regional filter coefficients, high computational speed, 2D filter mask operation, two-dimensional reconstruction filter masks, nonzero-valued pixels, inverse wavelet transform, arithmetic bit-shifting, integer addition operations, compression gain, Hilbert scanning, multiplierless 2D filter masks, image coding, image compression, convolution
43	Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro 0001	Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming.	DAC	2006	DBLP DOI BibTeX RDF	multiple constant multiplication, multiplierless digital filter design, delay optimization, area optimization
35	Min Li 0001, David Novo, Bruno Bougard, Frederik Naessens, Liesbet Van der Perre, Francky Catthoor	An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders.	SiPS	2008	DBLP DOI BibTeX RDF
35	Douglas L. Maskell, Achutavarrier Prasad Vinod, Graham S. Woods	Multiplierless multi-standard SDR channel filters.	MMSP	2008	DBLP DOI BibTeX RDF
35	J. Luis Tecpanecatl-Xihuitl, Ruth Aguilar-Ponce, Magdy A. Bayoumi	Hybrid multiplierless FIR filter architecture based on NEDA.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
35	Kishore A. Kotteri, Amy E. Bell, Joan Carletta	Multiplierless filter Bank design: structures that improve both hardware and image compression performance.	IEEE Trans. Circuits Syst. Video Technol.	2006	DBLP DOI BibTeX RDF
35	Raymond K. W. Chan, Moon-Chuen Lee	Multiplierless Fast DCT Algorithms with Minimal Approximation Errors.	ICPR (3)	2006	DBLP DOI BibTeX RDF
35	Go-An Rau, Meng-Xin Guo	Multiplierless Realization of Modified Comb Filter by Using Xilinx Spartan FPGAs.	ICICIC (2)	2006	DBLP DOI BibTeX RDF
35	Raymond K. W. Chan, Moon-Chuen Lee	Multiplierless Approximation of Fast DCT Algorithms.	ICME	2006	DBLP DOI BibTeX RDF
35	Uwe Meyer-Bäse, Jiajia Chen 0002, Chip-Hong Chang, Andrew G. Dempster	A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters.	APCCAS	2006	DBLP DOI BibTeX RDF
35	Valentina I. Anzova, Juha Yli-Kaakinen, Tapio Saramäki	An Algorithm for the Design of Multiplierless IIR Filters as a Parallel Connection of Two All-Pass Filters.	APCCAS	2006	DBLP DOI BibTeX RDF
35	Ming Z. Zhang, Vijayan K. Asari	A Fully Pipelined Multiplierless Architecture for 2D Convolution with Quadrant Symmetric Kernels.	APCCAS	2006	DBLP DOI BibTeX RDF
35	Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Ivan Saraiva Silva	A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor.	DSD	2005	DBLP DOI BibTeX RDF
35	Yasuhiro Takahashi, Michio Yokoyama	New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
35	Jun Wei Lee, Yong Ching Lim	A multiplierless filter bank with deep stopband suppression and narrow transition width.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
35	Fei Xu, Chip-Hong Chang, Ching-Chuen Jong	A new contention resolution algorithm for the design of minimal logic depth multiplierless filters.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
35	Mrinmoy Bhattacharya, Tapio Saramäki	Allpass structures for multiplierless realization of recursive digital filters.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
35	Mrinmoy Bhattacharya, Tapio Saramäki	Multiplierless implementation of bandpass and bandstop recursive digital filters using allpass structures.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
35	Juha Yli-Kaakinen, Tapio Saramäki	A systematic algorithm for the design of multiplierless FIR filters.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
35	Jinsong Mao, Wu-Sheng Lu, Shing-Chow Chan, Andreas Antoniou	Design and multiplierless implementation of two-channel biorthogonal IIR filter banks with low system delay.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
35	Mrinmoy Bhattacharya, Jaakko Astola	Multiplierless implementation of recursive digital filters based on coefficient translation methods in low sensitivity structures.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
35	Khurram Muhammad, Kaushik Roy 0001	A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters.	ISSS	1999	DBLP DOI BibTeX RDF
31	Carlos Salazar-Lazaro, Trac D. Tran	A Complexity Scalable Universal DCT Domain Image Resizing Algorithm.	IEEE Trans. Circuits Syst. Video Technol.	2007	DBLP DOI BibTeX RDF
31	Ya Jun Yu, Yong Ching Lim	Roundoff Noise Analysis of Signals Represented Using Signed Power-of-Two Terms.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
31	Robert Thomson 0003, Tughrul Arslan	Techniques for the evolution of pipelined linear transforms.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
31	Mohammed Javed Absar, Pol Marchal, Francky Catthoor	Data-Access Optimization of Embedded Systems Through Selective Inlining Transformation.	ESTIMedia	2005	DBLP DOI BibTeX RDF
31	Alen Docef, Faouzi Kossentini, Khanh Nguyen-Phi, Ismaeil R. Ismaeil	The quantized DCT and its application to DCT-based video coding.	IEEE Trans. Image Process.	2002	DBLP DOI BibTeX RDF
27	Levent Aksoy, Diego Jaccottet, Eduardo Costa 0001	Design of low complexity digital FIR filters.	SBCCI	2009	DBLP DOI BibTeX RDF	low-level synthesis, multiple constant multiplications, multiplierless filter design, high-level synthesis, array multipliers
27	Levent Aksoy, Ece Olcay Günes	An approximate algorithm for the multiple constant multiplications problem.	SBCCI	2008	DBLP DOI BibTeX RDF	graph-based technique, multiple constant multiplications problem, multiplierless filter design, approximate algorithm
27	Peter Tummeltshammer, James C. Hoe, Markus Püschel	Multiple constant multiplication by time-multiplexed mapping of addition chains.	DAC	2004	DBLP DOI BibTeX RDF	multiplierless, fusion, directed acyclic graph, addition chains
19	Saeed Haghiri, Salah I. Yahya, Abbas Rezaei, Arash Ahmadi	Multiplierless Implementation of Fitz-Hugh Nagumo (FHN) Modeling Using CORDIC Approach.	IEEE Trans. Emerg. Top. Comput. Intell.	2024	DBLP DOI BibTeX RDF
19	Charalampos Eleftheriadis, Georgios Chatzitsompanis, Georgios Karakonstantis	Enabling Voltage Over-Scaling in Multiplierless DSP Architectures via Algorithm-Hardware Co-Design.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
19	Jhilam Jana, Ritesh Sur Chowdhury, Sayan Tripathi, Jaydeb Bhaumik	FPGA implementation of compact and low-power multiplierless architectures for DWT and IDWT.	J. Real Time Image Process.	2024	DBLP DOI BibTeX RDF
19	Abhishek Ramdas Nair, Pallab Kumar Nath, Shantanu Chakrabartty, Chetan Singh Thakur	Multiplierless In-filter Computing for tinyML Platforms.	VLSID	2024	DBLP DOI BibTeX RDF
19	Charalampos Eleftheriadis, Georgios Karakonstantis	Optimal Adder-Multiplexer Co-Optimization for Time-Multiplexed Multiplierless Architectures.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
19	Martin Kumm, Anastasia Volkova, Silviu-Ioan Filip	Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
19	Saeed Haghiri, Salah I. Yahya, Abbas Rezaei, Arash Ahmadi	Multiplierless low-cost implementation of Hindmarsh-Rose neuron model in case of large-scale realization.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
19	Abhishek Ramdas Nair, Pallab Kumar Nath, Shantanu Chakrabartty, Chetan Singh Thakur	Multiplierless In-filter Computing for tinyML Platforms.	CoRR	2023	DBLP DOI BibTeX RDF
19	Levent Aksoy, Debapriya Basu Roy, Malik Imran, Samuel Pagliarini	Multiplierless Design of High-Speed Very Large Constant Multiplications.	CoRR	2023	DBLP DOI BibTeX RDF
19	Robson Domanski, William Kolodziejski, Wagner Penny, Marcelo Schiavon Porto, Bruno Zatt, Luciano Agostini	High-Throughput and Multiplierless Hardware Design for the AV1 Local Warped MC Interpolation.	ICIP	2023	DBLP DOI BibTeX RDF
19	Gordana Jovanovic-Dolecek, José M. de la Rosa 0001	Design of Wideband Multiplierless Compensators for Sharpened CIC Filters.	MWSCAS	2023	DBLP DOI BibTeX RDF
19	Robson Domanski, William Kolodziejski, Wagner Penny, Marcelo Schiavon Porto, Bruno Zatt, Luciano Agostini	High-Throughput and Multiplierless Hardware Design for the AV1 Fractional Motion Estimation.	LASCAS	2023	DBLP DOI BibTeX RDF
19	Abhishek Ramdas Nair, Pallab Kumar Nath, Shantanu Chakrabartty, Chetan Singh Thakur	Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
19	Fei Lyu 0002, Yan Xia, Zhelong Mao, Yanxu Wang, Yu Wang 0161, Yuanyong Luo	ML-PLAC: Multiplierless Piecewise Linear Approximation for Nonlinear Function Evaluation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
19	Jianming Cai, Han Bao 0001, Mo Chen, Quan Xu 0001, Bocheng Bao	Analog/Digital Multiplierless Implementations for Nullcline-Characteristics-Based Piecewise Linear Hindmarsh-Rose Neuron Model.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
19	Levent Aksoy, Debapriya Basu Roy, Malik Imran, Patrick Karl, Samuel Pagliarini	Multiplierless Design of Very Large Constant Multiplications in Cryptography.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
19	Ahmad Ghiasi, Abdulhamid Zahedi	Field-programmable gate arrays-based Morris-Lecar implementation using multiplierless digital approach and new divider-exponential modules.	Comput. Electr. Eng.	2022	DBLP DOI BibTeX RDF
19	Abdolvahab Khalili Sadaghiani, Samad Sheikhaei, Behjat Forouzandeh	Low Complexity Multiplierless Welch Estimator Based on Memory-Based FFT.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
19	A. Abinaya, M. Maheswari	Heuristic Analysis of Multiplierless Desensitized Half-Band Decimation Filter for Wireless Applications.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
19	Gordana Jovanovic-Dolecek	Comb decimator design based on symmetric polynomials with roots on the unit circle: Two-stage multiplierless design and improved magnitude characteristic.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
19	Aljosa Dudarin, Goran Molnar, Mladen Vucic	Optimum multiplierless sharpened cascaded-integrator-comb filters.	Digit. Signal Process.	2022	DBLP DOI BibTeX RDF
19	Guodao Zhang, Ruyu Liu, Yisu Ge, Abdulilah Mohammad Mayet, Sixian Chan, Guoqing Li, Ehsan Nazemi	Investigation on the Wilson Neuronal Model: Optimized Approximation and Digital Multiplierless Implementation.	IEEE Trans. Biomed. Circuits Syst.	2022	DBLP DOI BibTeX RDF
19	Levent Aksoy, Debapriya Basu Roy, Malik Imran, Patrick Karl, Samuel Pagliarini	Multiplierless Design of Very Large Constant Multiplications in Cryptography.	CoRR	2022	DBLP DOI BibTeX RDF
19	Rémi Garcia 0002, Anastasia Volkova, Martin Kumm, Alexandre Goldsztejn, Jonas Kühle	Hardware-Aware Design of Multiplierless Second-Order IIR Filters With Minimum Adders.	IEEE Trans. Signal Process.	2022	DBLP DOI BibTeX RDF
19	Marwan A. Fetteha, Wafaa S. Sayed, Lobna A. Said, Salwa K. Abd-El-Hafiz, Ahmed G. Radwan	Registerless Multiplierless YCoCg-R and YCoCg Color Space Converters Hardware Implementation.	ICCTA	2022	DBLP DOI BibTeX RDF
19	Gordana Jovanovic-Dolecek	Design of Multiplierless Wideband Compensator for Modified Cosine-Based Comb Decimator with Improved Aliasing Rejection.	MWSCAS	2022	DBLP DOI BibTeX RDF
19	Tobias Habermann, Jonas Kühle, Martin Kumm, Anastasia Volkova	Hardware-Aware Quantization for Multiplierless Neural Network Controllers.	APCCAS	2022	DBLP DOI BibTeX RDF
19	Malik S. A., Ajaz Hussain Mir	Discrete Multiplierless Implementation of Fractional Order Hindmarsh-Rose Model.	IEEE Trans. Emerg. Top. Comput. Intell.	2021	DBLP DOI BibTeX RDF
19	Seyed Hadi Mirfarshbafan, Sueda Taner, Christoph Studer	SMUL-FFT: A Streaming Multiplierless Fast Fourier Transform.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
19	Abhishek Ramdas Nair, Pallab Kumar Nath, Shantanu Chakrabartty, Chetan Singh Thakur	Multiplierless MP-Kernel Machine For Energy-efficient Edge Devices.	CoRR	2021	DBLP BibTeX RDF
19	Rémi Garcia 0002, Anastasia Volkova, Martin Kumm, Alexandre Goldsztejn, Jonas Kühle	Hardware-aware Design of Multiplierless Second-Order IIR Filters with Minimum Adders.	CoRR	2021	DBLP BibTeX RDF
19	Nguyen T. Thao, Dominik Rzepka	Time Encoding of Bandlimited Signals: Reconstruction by Pseudo-Inversion and Time-Varying Multiplierless FIR Filtering.	IEEE Trans. Signal Process.	2021	DBLP DOI BibTeX RDF
19	S. Skandha Deepsita, Kuchipudi Divya, Sk. Noor Mahammad	Energy Efficient and Multiplierless Approximate Integer DCT Implementation for HEVC.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
19	Vladislav A. Lesnikov, Tatiana V. Naumovich, Alexander V. Chastikov	Multiplierless IIR Filter Design Technique.	MECO	2021	DBLP DOI BibTeX RDF
19	Lulin Cai, Yiduan Qian, Yajuan He, Wen Feng	Design of Approximate Multiplierless DCT with CSD Encoding for Image Processing.	ISCAS	2021	DBLP DOI BibTeX RDF
19	AlaaEddin Loulou, Juha Yli-Kaakinen, Toni Levanen, Vesa Lehtinen, Frank Schaich, Thorsten Wild, Markku Renfors, Mikko Valkama	Multiplierless Filtered-OFDM Transmitter for Narrowband IoT Devices.	IEEE Internet Things J.	2020	DBLP DOI BibTeX RDF
19	N. Sajwan, Ila Sharma, Anil Kumar 0001, L. K. Balyan	Performance of Multiplierless FIR Filter Based on Directed Minimal Spanning Tree: A Comparative Study.	Circuits Syst. Signal Process.	2020	DBLP DOI BibTeX RDF
19	Anirban Chakraborty 0004, Ayan Banerjee 0003	A Memory Efficient, Multiplierless & Modular VLSI Architecture of 1D/2D Re-Configurable 9/7 & 5/3 DWT Filters Using Distributed Arithmetic.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
19	Yashrajsinh Parmar, K. Sridharan 0001	A Resource-Efficient Multiplierless Systolic Array Architecture for Convolutions in Deep Networks.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
19	Wallace A. Martins, M. R. Bhavani Shankar, Björn E. Ottersten	Oversampled DFT-Modulated Biorthogonal Filter Banks: Perfect Reconstruction Designs and Multiplierless Approximations.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
19	Gordana Jovanovic-Dolecek, Luis A. Camuñas-Mesa, José M. de la Rosa 0001	Low Order Wideband Multiplierless Comb Compensator.	MWSCAS	2020	DBLP DOI BibTeX RDF
19	Luiz Felipe da Silveira Coelho, Lisandro Lovisolo, Michel Pompeu Tcheou	A Proposal for Multiplierless RLS Adaptive Filters with Implementation Complexity Constraint.	ISCAS	2020	DBLP DOI BibTeX RDF
19	Vishnu P. Nambiar, Eng-Kiat Koh, Junran Pu, Aarthy Mani, Ming Ming Wong, Li Fei, Wang Ling Goh, Anh Tuan Do	Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model.	ISCAS	2020	DBLP DOI BibTeX RDF
19	Sebastian A. A. Vogel	Design and implementation of number representations for efficient multiplierless acceleration of convolutional neural networks.		2020	RDF
19	Supriya Dhabal, Palaniandavar Venkateswaran	An Improved Global-Best-Guided Cuckoo Search Algorithm for Multiplierless Design of Two-Dimensional IIR Filters.	Circuits Syst. Signal Process.	2019	DBLP DOI BibTeX RDF
19	Xiaobai Chen, Jinglong Xu, Zhiyi Yu	A 68-mw 2.2 Tops/w Low Bit Width and Multiplierless DCNN Object Detection Processor for Visually Impaired People.	IEEE Trans. Circuits Syst. Video Technol.	2019	DBLP DOI BibTeX RDF
19	Nazreen P. M., Shantanu Chakrabartty, Chetan Singh Thakur	Multiplierless and Sparse Machine Learning based on Margin Propagation Networks.	CoRR	2019	DBLP BibTeX RDF
19	Abdulhamid Zahedi, Saeed Haghiri, Mohsen Hayati	Multiplierless Digital Implementation of Time-Varying FitzHugh-Nagumo Model.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
19	Sebastian Vogel, Jannik Springer, Andre Guntoro, Gerd Ascheid	Self-Supervised Quantization of Pre-Trained Neural Networks for Multiplierless Acceleration.	DATE	2019	DBLP DOI BibTeX RDF
19	Jinti Hazarika, Mohd. Tasleem Khan, Shaik Rafi Ahamed, Harshal B. Nemade	High Performance Multiplierless Serial Pipelined VLSI Architecture for Real-Valued FFT.	NCC	2019	DBLP DOI BibTeX RDF
19	Taizo Suzuki, Seisuke Kyochi, Yuichi Tanaka 0001, Masaaki Ikehara	Multiplierless lifting-based fast X transforms derived from fast Hartley transform factorization.	Multidimens. Syst. Signal Process.	2018	DBLP DOI BibTeX RDF