Search results for "multiply-accumulate"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
198	Paul F. Stelling, Vojin G. Oklobdzija	Implementing Multiply-Accumulate Operation in Multiplication Time.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	multiply-accumulate operation, multiplication time, optimal delays, instruction time, optimal multiply-accumulate circuit, RISC CPU, partial product reduction tree, final adder, digital signal processing, power savings, multiplying circuits, circuit design, VLSI circuits, parallel multiplier, processor performance, video applications, graphics applications, clock speed
116	Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga	Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline.	ASAP	1996	DBLP DOI BibTeX RDF	floating point multiply-accumulate unit, three-dimensional graphics engines, normalized space, virtual reality, virtual reality, parallelism, computer graphics, scientific visualization, matrix multiplication, matrix multiplications, data visualisation, floating point arithmetic, architectural optimizations, graphics pipeline
79	Albert Danysh, Dimitri Tan	Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	data-path design, multiply-accumulate, Booth, Wallace, unsigned, multimedia, VLSI, Parallel, MAC, SIMD, vector, fixed-point, multiplier, high-speed arithmetic, signed, integer
64	Laszlo Hars	Long Modular Multiplication for Cryptographic Applications.	CHES	2004	DBLP DOI BibTeX RDF	Quisquater multiplication, multiply-accumulate architecture, optimization, cryptography, Computer arithmetic, Montgomery multiplication, reciprocal, modular multiplication, Modular reduction
64	Zhen Luo, Margaret Martonosi	Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Delayed addition, multiply-accumulate, FPGA, MAC, accumulation
64	V. Visvanathan, S. Ramanathan	A modular systolic architecture for delayed least mean squares adaptive filtering.	VLSI Design	1995	DBLP DOI BibTeX RDF	modular systolic architecture, delayed least mean squares adaptive filtering, coefficient adaptation, input sampling periods, output latency, convergence behavior, systolization technique, maximum sampling rate, multiply-accumulate processor modules, systolic arrays, pipeline processing, adaptive filters, convergence of numerical methods, least mean squares methods
62	Moboluwaji O. Sanu, Earl E. Swartzlander Jr.	Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields.	ASAP	2005	DBLP DOI BibTeX RDF
53	Ahmed Abdelgawad 0001, Magdy A. Bayoumi	High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
53	Subhadeep Roy	A sub-word-parallel Galois field multiply-accumulate unit for digital signal processors.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
46	Mark G. Arnold	A VLIW Architecture for Logarithmic Arithmetic.	DSD	2003	DBLP DOI BibTeX RDF	Very Long Instruction Word, sum of products, pipeline, Logarithmic Number System
45	Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik	A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.	VLSI Design	2010	DBLP DOI BibTeX RDF	multiply-accumulate, Fused and continuous MAC, VLSI, Floating-point
38	Shai Erez, Guy Even	An improved micro-architecture for function approximation using piecewise quadratic interpolation.	ICCD	2008	DBLP DOI BibTeX RDF
38	Mustafa Aktan, Günhan Dündar	Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming.	PATMOS	2005	DBLP DOI BibTeX RDF
38	Mattias Duppils, Christer Svensson	Low power mixed analog-digital signal processing.	ISLPED	2000	DBLP DOI BibTeX RDF
34	Neha Ashar, Gopal Raut, Vasundhara Trivedi, Santosh Kumar Vishvakarma, Akash Kumar 0001	QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit.	IEEE Access	2024	DBLP DOI BibTeX RDF
34	Harideep Nair, Prabhu Vellaisamy, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen	OzMAC: An Energy-Efficient Sparsity-Exploiting Multiply-Accumulate-Unit Design for DL Inference.	CoRR	2024	DBLP DOI BibTeX RDF
34	Jeyakumar Ponraj, R. Jeyabharath, P. Veena, Tharumar Srihari	High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system.	Integr.	2023	DBLP DOI BibTeX RDF
34	S. Skandha Deepsita, T. Karthikeyan, Sk. Noor Mahammad	Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications.	Integr.	2023	DBLP DOI BibTeX RDF
34	Pedro Sartori Locatelli, Dalton Martini Colombo, Kamal El-Sankary	Time-Domain Multiply-Accumulate Unit.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
34	Raphael Nägele, Jakob Finkbeiner, Valentin Stadtlander, Markus Grözing, Manfred Berroth	Analog Multiply-Accumulate Cell With Multi-Bit Resolution for All-Analog AI Inference Accelerators.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
34	Wenjie Li 0003, Aokun Hu, Gang Wang, Ningyi Xu, Guanghui He	Low-Complexity Precision-Scalable Multiply-Accumulate Unit Architectures for Deep Neural Network Accelerators.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
34	Pavel A. Lyakhov	Area-Efficient digital filtering based on truncated multiply-accumulate units in residue number system 2n-1,2n,2n+1.	J. King Saud Univ. Comput. Inf. Sci.	2023	DBLP DOI BibTeX RDF
34	Yuzong Chen, Mohamed S. Abdelfattah	BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs.	CoRR	2023	DBLP DOI BibTeX RDF
34	Raphael Cardoso, Clément Zrounba, Mohab Abdalla, Paul Jiménez, Mauricio Gomes de Queiroz, Benoît Charbonnier, Fabio Pavanello, Ian O'Connor, Sébastien Le Beux	Towards a Robust Multiply-Accumulate Cell in Photonics using Phase-Change Materials.	DATE	2023	DBLP DOI BibTeX RDF
34	Yuzong Chen, Mohamed S. Abdelfattah	BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs.	FCCM	2023	DBLP DOI BibTeX RDF
34	Subhali Subhechha, Stefan Cosemans, Attilio Belmonte, Nouredine Rassoul, Shamin Houshmand Sharifi, Peter Debacker, Diederik Verkest, Romain Delhougne, Gouri Sankar Kar	Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays.	IMW	2023	DBLP DOI BibTeX RDF
34	Lorenzo De Marinis, P. S. Kincaid, Giampiero Contestabile, S. Gupta, Nicola Andriolli	Graphene-Based Photonic-Electronic Multiply-Accumulate Neurons.	PSC	2023	DBLP DOI BibTeX RDF
34	Hanyu Shi, Yuejun Zhang, Huihong Zhang, Qikang Li, Pengjun Wang	Ternary Multiply-Accumulate Circuit Based on Domino Structure.	ASICON	2023	DBLP DOI BibTeX RDF
34	Yuechen Lu, Weifeng Liu 0002	DASP: Specific Dense Matrix Multiply-Accumulate Units Accelerated General Sparse Matrix-Vector Multiplication.	SC	2023	DBLP DOI BibTeX RDF
34	Sandeep Soni, Gaurav Verma, Alok Kumar Shukla, Brajesh Kumar Kaushik	Energy Efficient DSHE based Analogue Multiply Accumulate Computing Crossbar Architecture.	APCCAS	2023	DBLP DOI BibTeX RDF
34	Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida	A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks.	IPSJ Trans. Syst. LSI Des. Methodol.	2022	DBLP DOI BibTeX RDF
34	Harsh Chhajed, Gopal Raut, Narendra Singh Dhakad, Sudheer Vishwakarma, Santosh Kumar Vishvakarma	BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
34	Peter Schober, M. Hassan Najafi, Nima TaheriNejad	High-Accuracy Multiply-Accumulate (MAC) Technique for Unary Stochastic Computing.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
34	S. Rakesh, K. S. Vijula Grace	Low Power Transposed Form 4-Tap Finite Impulse Response Filter Using Power Efficient Multiply Accumulate Unit.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
34	Mariko Tatsumi, Silviu-Ioan Filip, Caroline White, Olivier Sentieys, Guy Lemieux	Mixing Low-Precision Formats in Multiply-Accumulate Units for DNN Training.	FPT	2022	DBLP DOI BibTeX RDF
34	Hongbing Tan, Run Yan, Ling Yang, Libo Huang, Liquan Xiao, Qianming Yang	Efficient Multiple-Precision and Mixed-Precision Floating-Point Fused Multiply-Accumulate Unit for HPC and AI Applications.	ICA3PP	2022	DBLP DOI BibTeX RDF
34	Jian Chen, Xinru Zhou, Xinhe Li, Lijie Wang, Shengli Lu, Hao Liu	Design of Precision Configurable Multiply Accumulate Unit for Neural Network Accelerator.	AIoTC	2022	DBLP BibTeX RDF
34	Haochuan Wan, Chaolin Rao, Yueyang Zheng, Pingqiang Zhou, Xin Lou	SME: A Systolic Multiply-accumulate Engine for MLP-based Neural Network.	APCCAS	2022	DBLP DOI BibTeX RDF
34	Young Seo Lee, Kyung Min Kim, Ji Heon Lee, Young-Ho Gong, Seon Wook Kim, Sung Woo Chung	Monolithic 3D stacked multiply-accumulate units.	Integr.	2021	DBLP DOI BibTeX RDF
34	Mohammadreza Esmali Nojehdeh, Sajjad Parvin, Mustafa Altun	Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks.	ISVLSI	2021	DBLP DOI BibTeX RDF
34	Sandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine	P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor.	VLSID	2021	DBLP DOI BibTeX RDF
34	Che-Wei Tung, Shih-Hsu Huang	A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process.	IEEE Access	2020	DBLP DOI BibTeX RDF
34	Song-Nien Tang, Yu-Shin Han	A High-Accuracy Hardware-Efficient Multiply-Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs.	IEEE Access	2020	DBLP DOI BibTeX RDF
34	Pavel Alekseevich Lyakhov, Maria V. Valueva, Georgii V. Valuev, Nikolay N. Nagornov	High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System.	IEEE Access	2020	DBLP DOI BibTeX RDF
34	Mallika Rathore, Peter A. Milder, Emre Salman	Error Probability Models for Voltage-Scaled Multiply-Accumulate Units.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
34	Hao Zhang 0041, Dongdong Chen 0002, Seok-Bum Ko	New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference.	IEEE Trans. Computers	2020	DBLP DOI BibTeX RDF
34	Mohammadreza Esmali Nojehdeh, Levent Aksoy, Mustafa Altun	Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks.	ISVLSI	2020	DBLP DOI BibTeX RDF
34	Nuno Neves 0002, Pedro Tomás, Nuno Roma	Dynamic Fused Multiply-Accumulate Posit Unit with Variable Exponent Size for Low-Precision DSP Applications.	SiPS	2020	DBLP DOI BibTeX RDF
34	S. Ashwin Balagopal, Janakiraman Viraraghavan	Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study.	ISCAS	2020	DBLP DOI BibTeX RDF
34	Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler	Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars.	ISCAS	2020	DBLP DOI BibTeX RDF
34	Yucong Huang, Zhitao Yang, Jianghan Zhu, Terry Tao Ye	Analog Circuit Implementation of Neurons with Multiply-Accumulate and ReLU Functions.	ACM Great Lakes Symposium on VLSI	2020	DBLP DOI BibTeX RDF
34	Hongwei Xie, Yafei Song, Ling Cai, Mingyang Li	Overflow Aware Quantization: Accelerating Neural Network Inference by Low-bit Multiply-Accumulate Operations.	IJCAI	2020	DBLP DOI BibTeX RDF
34	Mahmoud Masadeh, Osman Hasan, Sofiène Tahar	Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency.	IEEE Access	2019	DBLP DOI BibTeX RDF
34	Sungju Ryu, Naebeom Park, Jae-Joon Kim	Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
34	Ismail Gassoumi, Lamjed Touil, Bouraoui Ouni	Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
34	Dongyeob Shin, Wonseok Choi 0004, Jongsun Park 0001, Swaroop Ghosh	Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2019	DBLP DOI BibTeX RDF
34	Vincent Camus, Linyan Mei, Christian C. Enz, Marian Verhelst	Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2019	DBLP DOI BibTeX RDF
34	Tongxin Yang, Toshinori Sato, Tomoaki Ukezono	An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area.	ISVLSI	2019	DBLP DOI BibTeX RDF
34	Andrew Boutros, Mohamed Eldafrawy, Sadegh Yazdanshenas, Vaughn Betz	Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
34	Ziwei Wang, Martin A. Trefzer, Simon J. Bale, Andy M. Tyrrell	Approximate Multiply-Accumulate Array for Convolutional Neural Networks on FPGA.	ReCoSoC	2019	DBLP DOI BibTeX RDF
34	Vincent Camus, Christian C. Enz, Marian Verhelst	Survey of Precision-Scalable Multiply-Accumulate Units for Neural-Network Processing.	AICAS	2019	DBLP DOI BibTeX RDF
34	Hao Zhang 0041, Jiongrui He, Seok-Bum Ko	Efficient Posit Multiply-Accumulate Unit Generator for Deep Learning Applications.	ISCAS	2019	DBLP DOI BibTeX RDF
34	Xinyue Zhang 0002, Yuan Wang 0001, Yawen Zhang, Jiahao Song, Zuodong Zhang, Kaili Cheng, Runsheng Wang, Ru Huang	Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing.	ICICDT	2019	DBLP DOI BibTeX RDF
34	Xinyue Zhang 0002, Jiahao Song, Yuan Wang 0001, Yawen Zhang, Zuodong Zhang, Runsheng Wang, Ru Huang	An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing.	ASICON	2019	DBLP DOI BibTeX RDF
34	M. Mohamed Asan Basiri	Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit.	VDAT	2019	DBLP DOI BibTeX RDF
34	Dong-Ik Jeon, Kyeong-Bin Park, Ki-Seok Chung	HMC-MAC: Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube.	IEEE Comput. Archit. Lett.	2018	DBLP DOI BibTeX RDF
34	James Garland, David Gregg	Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing.	ACM Trans. Archit. Code Optim.	2018	DBLP DOI BibTeX RDF
34	James Garland, David Gregg	Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing.	CoRR	2018	DBLP BibTeX RDF
34	Vassilis Paliouras, Konstantina Karagianni, Yann Oster	Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State Machines.	PATMOS	2018	DBLP DOI BibTeX RDF
34	William Kamp, Norbert Abel, Gianni Comoretto	Complex Multiply Accumulate Cells for the Square Kilometre Array Correlators.	ReConFig	2018	DBLP DOI BibTeX RDF
34	Ahmed Saeed 0005, Kareem Mansour	Implementation of Low-Power Multiply-Accumulate (MAC) Unit for IoT Processors.	EECS	2018	DBLP DOI BibTeX RDF
34	Hao Zhang 0041, Hyuk Jae Lee, Seok-Bum Ko	Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors.	ISCAS	2018	DBLP DOI BibTeX RDF
34	Siam U. Hussain, Bita Darvish Rouhani, Mohammad Ghasemzadeh 0002, Farinaz Koushanfar	MAXelerator: FPGA accelerator for privacy preserving multiply-accumulate (MAC) on cloud servers.	DAC	2018	DBLP DOI BibTeX RDF
34	James Garland, David Gregg	Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks.	IEEE Comput. Archit. Lett.	2017	DBLP DOI BibTeX RDF
34	M. Mohamed Asan Basiri, S. K. Noor Mohammad	Quadruple throughput fixed point quarter precision multiply accumulate circuit design.	IET Comput. Digit. Tech.	2017	DBLP DOI BibTeX RDF
34	James Garland, David Gregg	Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks.	CoRR	2016	DBLP BibTeX RDF
34	Lukas Gerlach 0001, Guillermo Payá Vayá, Holger Blume	An area efficient real- and complex-valued multiply-accumulate SIMD unit for digital signal processors.	SiPS	2015	DBLP DOI BibTeX RDF
34	Rohit Kumar, Manisha Pattanaik	A novel dual multiplier floating point multiply accumulate architecture.	VDAT	2015	DBLP DOI BibTeX RDF
34	Nasibeh Nasiri, Oren Segal, Martin Margala	Modified fused multiply-accumulate chained unit.	MWSCAS	2014	DBLP DOI BibTeX RDF
34	Suresh Srinivasan, Ketan Bhudiya, Rajaraman Ramanarayanan, P. Sahit Babu, Tiju Jacob, Sanu Mathew, Ram Krishnamurthy 0001, Vasantha Erraguntla	Split-Path Fused Floating Point Multiply Accumulate (FPMAC).	IEEE Symposium on Computer Arithmetic	2013	DBLP DOI BibTeX RDF
34	R. Sakthivel 0002, K. Sravanthi, Harish M. Kittur	Low power energy efficient pipelined multiply-accumulate architecture.	ICACCI	2012	DBLP DOI BibTeX RDF
34	Tobias Vejda, Johann Großschädl, Dan Page	A Unified Multiply/Accumulate Unit for Pairing-Based Cryptography over Prime, Binary and Ternary Fields.	DSD	2011	DBLP DOI BibTeX RDF
34	Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors	A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
34	Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors	Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements.	IPDPS	2009	DBLP DOI BibTeX RDF
34	Shanthala S., Cyril Raj, S. Y. Kulkarni	Design and VLSI Implementation of Pipelined Multiply Accumulate Unit.	ICETET	2009	DBLP DOI BibTeX RDF
34	Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors	High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture.	SoCC	2009	DBLP DOI BibTeX RDF
34	Fatemeh Kashfi, Sied Mehdi Fakhraie, Saeed Safari	Designing an ultra-high-speed multiply-accumulate structure.	Microelectron. J.	2008	DBLP DOI BibTeX RDF
34	Erik Lindahl, Oscar Gustafsson	Architecture-aware design of a decimation filter based on a dual wordlength multiply-accumulate unit.	ACSCC	2008	DBLP DOI BibTeX RDF
34	Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis	Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications.	Integr.	2007	DBLP DOI BibTeX RDF
34	William Kamp, Andrew Bainbridge-Smith	Multiply Accumulate Unit Optimised for Fast Dot-Product Evaluation.	FPT	2007	DBLP DOI BibTeX RDF
34	Ayman A. Fayed, Walid Elgharbawy, Magdy A. Bayoumi	A data merging technique for high-speed low-power multiply accumulate units.	ICASSP (5)	2004	DBLP DOI BibTeX RDF
34	Johann Großschädl, Guy-Armand Kamendje	A single-cycle (32×32+32+64)-bit multiply/accumulate unit for digital signal processing and public-key cryptography.	ICECS	2003	DBLP DOI BibTeX RDF
34	James T. Kao, Masayuki Miyazaki, Anantha P. Chandrakasan	A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
34	Yuyun Liao, David B. Roberts	A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
34	William G. Natter, Behrouz Nowrouzian	A novel multiplier recoding technique and its application to the development of a high-speed parallel online multiply-accumulate architecture.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
34	Adimathara P. Preethy, Damu Radhakrishnan, Amos Omondi	A high performance RNS multiply-accumulate unit.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
34	Dusan Suvakovic, C. André T. Salama	A pipelined multiply-accumulate unit design for energy recovery DSP systems.	ISCAS	2000	DBLP DOI BibTeX RDF
34	William G. Natter, Behrouz Nowrouzian	A novel algorithm for signed-digit online multiply-accumulate operation and its purely signed-binary hardware implementation.	ISCAS	2000	DBLP DOI BibTeX RDF
34	Adimathara P. Preethy	High performance multiply-accumulate unit for residue number system DSP core		2000	RDF
34	Christian D. Nielsen, Alain J. Martin	Design of a delay-insensitive multiply-accumulate unit.	Integr.	1993	DBLP DOI BibTeX RDF