Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
198 | Paul F. Stelling, Vojin G. Oklobdzija |
Implementing Multiply-Accumulate Operation in Multiplication Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 99-, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multiply-accumulate operation, multiplication time, optimal delays, instruction time, optimal multiply-accumulate circuit, RISC CPU, partial product reduction tree, final adder, digital signal processing, power savings, multiplying circuits, circuit design, VLSI circuits, parallel multiplier, processor performance, video applications, graphics applications, clock speed |
116 | Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga |
Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 65-71, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
floating point multiply-accumulate unit, three-dimensional graphics engines, normalized space, virtual reality, virtual reality, parallelism, computer graphics, scientific visualization, matrix multiplication, matrix multiplications, data visualisation, floating point arithmetic, architectural optimizations, graphics pipeline |
79 | Albert Danysh, Dimitri Tan |
Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(3), pp. 284-293, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
data-path design, multiply-accumulate, Booth, Wallace, unsigned, multimedia, VLSI, Parallel, MAC, SIMD, vector, fixed-point, multiplier, high-speed arithmetic, signed, integer |
64 | Laszlo Hars |
Long Modular Multiplication for Cryptographic Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004. Proceedings, pp. 45-61, 2004, Springer, 3-540-22666-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Quisquater multiplication, multiply-accumulate architecture, optimization, cryptography, Computer arithmetic, Montgomery multiplication, reciprocal, modular multiplication, Modular reduction |
64 | Zhen Luo, Margaret Martonosi |
Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(3), pp. 208-218, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Delayed addition, multiply-accumulate, FPGA, MAC, accumulation |
64 | V. Visvanathan, S. Ramanathan |
A modular systolic architecture for delayed least mean squares adaptive filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 332-337, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
modular systolic architecture, delayed least mean squares adaptive filtering, coefficient adaptation, input sampling periods, output latency, convergence behavior, systolization technique, maximum sampling rate, multiply-accumulate processor modules, systolic arrays, pipeline processing, adaptive filters, convergence of numerical methods, least mean squares methods |
62 | Moboluwaji O. Sanu, Earl E. Swartzlander Jr. |
Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 134-139, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
53 | Ahmed Abdelgawad 0001, Magdy A. Bayoumi |
High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3199-3202, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
53 | Subhadeep Roy |
A sub-word-parallel Galois field multiply-accumulate unit for digital signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1626-1629, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Mark G. Arnold |
A VLIW Architecture for Logarithmic Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 294-303, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Very Long Instruction Word, sum of products, pipeline, Logarithmic Number System |
45 | Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik |
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 252-257, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multiply-accumulate, Fused and continuous MAC, VLSI, Floating-point |
38 | Shai Erez, Guy Even |
An improved micro-architecture for function approximation using piecewise quadratic interpolation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 422-426, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Mustafa Aktan, Günhan Dündar |
Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 137-145, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Mattias Duppils, Christer Svensson |
Low power mixed analog-digital signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 61-66, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Neha Ashar, Gopal Raut, Vasundhara Trivedi, Santosh Kumar Vishvakarma, Akash Kumar 0001 |
QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 43600-43614, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
34 | Harideep Nair, Prabhu Vellaisamy, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen |
OzMAC: An Energy-Efficient Sparsity-Exploiting Multiply-Accumulate-Unit Design for DL Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2402.19376, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
34 | Jeyakumar Ponraj, R. Jeyabharath, P. Veena, Tharumar Srihari |
High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 93, pp. 102055, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | S. Skandha Deepsita, T. Karthikeyan, Sk. Noor Mahammad |
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 92, pp. 24-34, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Pedro Sartori Locatelli, Dalton Martini Colombo, Kamal El-Sankary |
Time-Domain Multiply-Accumulate Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(6), pp. 762-775, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Raphael Nägele, Jakob Finkbeiner, Valentin Stadtlander, Markus Grözing, Manfred Berroth |
Analog Multiply-Accumulate Cell With Multi-Bit Resolution for All-Analog AI Inference Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(9), pp. 3509-3521, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Wenjie Li 0003, Aokun Hu, Gang Wang, Ningyi Xu, Guanghui He |
Low-Complexity Precision-Scalable Multiply-Accumulate Unit Architectures for Deep Neural Network Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(4), pp. 1610-1614, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Pavel A. Lyakhov |
Area-Efficient digital filtering based on truncated multiply-accumulate units in residue number system 2n-1,2n,2n+1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. King Saud Univ. Comput. Inf. Sci. ![In: J. King Saud Univ. Comput. Inf. Sci. 35(6), pp. 101574, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Yuzong Chen, Mohamed S. Abdelfattah |
BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.03974, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Raphael Cardoso, Clément Zrounba, Mohab Abdalla, Paul Jiménez, Mauricio Gomes de Queiroz, Benoît Charbonnier, Fabio Pavanello, Ian O'Connor, Sébastien Le Beux |
Towards a Robust Multiply-Accumulate Cell in Photonics using Phase-Change Materials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, pp. 1-2, 2023, IEEE, 978-3-9819263-7-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Yuzong Chen, Mohamed S. Abdelfattah |
BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2023, Marina Del Rey, CA, USA, May 8-11, 2023, pp. 52-62, 2023, IEEE, 979-8-3503-1205-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Subhali Subhechha, Stefan Cosemans, Attilio Belmonte, Nouredine Rassoul, Shamin Houshmand Sharifi, Peter Debacker, Diederik Verkest, Romain Delhougne, Gouri Sankar Kar |
Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMW ![In: IEEE International Memory Workshop, IMW 2023, Monterey, CA, USA, May 21-24, 2023, pp. 1-4, 2023, IEEE, 978-1-6654-7459-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Lorenzo De Marinis, P. S. Kincaid, Giampiero Contestabile, S. Gupta, Nicola Andriolli |
Graphene-Based Photonic-Electronic Multiply-Accumulate Neurons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PSC ![In: International Conference on Photonics in Switching and Computing, PSC 2023, Mantova, Italy, September 26-29, 2023, pp. 1-3, 2023, IEEE, 979-8-3503-2370-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Hanyu Shi, Yuejun Zhang, Huihong Zhang, Qikang Li, Pengjun Wang |
Ternary Multiply-Accumulate Circuit Based on Domino Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 15th IEEE International Conference on ASIC, ASICON 2023, Nanjing, China, October 24-27, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-1298-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Yuechen Lu, Weifeng Liu 0002 |
DASP: Specific Dense Matrix Multiply-Accumulate Units Accelerated General Sparse Matrix-Vector Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2023, Denver, CO, USA, November 12-17, 2023, pp. 73:1-73:14, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Sandeep Soni, Gaurav Verma, Alok Kumar Shukla, Brajesh Kumar Kaushik |
Energy Efficient DSHE based Analogue Multiply Accumulate Computing Crossbar Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, India, November 19-22, 2023, pp. 21-25, 2023, IEEE, 979-8-3503-8119-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
34 | Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida |
A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 15, pp. 16-19, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
34 | Harsh Chhajed, Gopal Raut, Narendra Singh Dhakad, Sudheer Vishwakarma, Santosh Kumar Vishvakarma |
BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 41(4), pp. 2045-2060, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
34 | Peter Schober, M. Hassan Najafi, Nima TaheriNejad |
High-Accuracy Multiply-Accumulate (MAC) Technique for Unary Stochastic Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 71(6), pp. 1425-1439, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
34 | S. Rakesh, K. S. Vijula Grace |
Low Power Transposed Form 4-Tap Finite Impulse Response Filter Using Power Efficient Multiply Accumulate Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(1), pp. 2250016:1-2250016:15, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
34 | Mariko Tatsumi, Silviu-Ioan Filip, Caroline White, Olivier Sentieys, Guy Lemieux |
Mixing Low-Precision Formats in Multiply-Accumulate Units for DNN Training. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: International Conference on Field-Programmable Technology, (IC)FPT 2022, Hong Kong, December 5-9, 2022, pp. 1-9, 2022, IEEE, 978-1-6654-5336-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
34 | Hongbing Tan, Run Yan, Ling Yang, Libo Huang, Liquan Xiao, Qianming Yang |
Efficient Multiple-Precision and Mixed-Precision Floating-Point Fused Multiply-Accumulate Unit for HPC and AI Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP ![In: Algorithms and Architectures for Parallel Processing - 22nd International Conference, ICA3PP 2022, Copenhagen, Denmark, October 10-12, 2022, Proceedings, pp. 642-659, 2022, Springer, 978-3-031-22676-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
34 | Jian Chen, Xinru Zhou, Xinhe Li, Lijie Wang, Shengli Lu, Hao Liu |
Design of Precision Configurable Multiply Accumulate Unit for Neural Network Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AIoTC ![In: Proceedings of the 2022 International Conference on Artificial Intelligence, Internet of Things and Cloud Computing Technology, Virtual Event, Fuzhou, China, October 21-23, 2022., Virtual Event, Fuzhou, China, October 21-23, 2022., pp. 29-39, 2022, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
34 | Haochuan Wan, Chaolin Rao, Yueyang Zheng, Pingqiang Zhou, Xin Lou |
SME: A Systolic Multiply-accumulate Engine for MLP-based Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuit and Systems, APCCAS 2022, Shenzhen, China, November 11-13, 2022, pp. 270-274, 2022, IEEE, 978-1-6654-5073-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
34 | Young Seo Lee, Kyung Min Kim, Ji Heon Lee, Young-Ho Gong, Seon Wook Kim, Sung Woo Chung |
Monolithic 3D stacked multiply-accumulate units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 76, pp. 183-189, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
34 | Mohammadreza Esmali Nojehdeh, Sajjad Parvin, Mustafa Altun |
Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, FL, USA, July 7-9, 2021, pp. 402-405, 2021, IEEE, 978-1-6654-3946-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
34 | Sandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine |
P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, VLSID 2021, Guwahati, India, February 20-24, 2021, pp. 282-287, 2021, IEEE, 978-1-6654-4087-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
34 | Che-Wei Tung, Shih-Hsu Huang |
A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 87367-87377, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Song-Nien Tang, Yu-Shin Han |
A High-Accuracy Hardware-Efficient Multiply-Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 214716-214731, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Pavel Alekseevich Lyakhov, Maria V. Valueva, Georgii V. Valuev, Nikolay N. Nagornov |
High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 209181-209190, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Mallika Rathore, Peter A. Milder, Emre Salman |
Error Probability Models for Voltage-Scaled Multiply-Accumulate Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(7), pp. 1665-1675, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Hao Zhang 0041, Dongdong Chen 0002, Seok-Bum Ko |
New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 69(1), pp. 26-38, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Mohammadreza Esmali Nojehdeh, Levent Aksoy, Mustafa Altun |
Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020, Limassol, Cyprus, July 6-8, 2020, pp. 96-101, 2020, IEEE, 978-1-7281-5775-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Nuno Neves 0002, Pedro Tomás, Nuno Roma |
Dynamic Fused Multiply-Accumulate Posit Unit with Variable Exponent Size for Low-Precision DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: IEEE Workshop on Signal Processing Systems, SiPS 2020, Coimbra, Portugal, October 20-22, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-8100-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | S. Ashwin Balagopal, Janakiraman Viraraghavan |
Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler |
Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Yucong Huang, Zhitao Yang, Jianghan Zhu, Terry Tao Ye |
Analog Circuit Implementation of Neurons with Multiply-Accumulate and ReLU Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '20: Great Lakes Symposium on VLSI 2020, Virtual Event, China, September 7-9, 2020, pp. 493-498, 2020, ACM, 978-1-4503-7944-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Hongwei Xie, Yafei Song, Ling Cai, Mingyang Li |
Overflow Aware Quantization: Accelerating Neural Network Inference by Low-bit Multiply-Accumulate Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCAI ![In: Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, IJCAI 2020, pp. 868-875, 2020, ijcai.org. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Mahmoud Masadeh, Osman Hasan, Sofiène Tahar |
Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 147129-147142, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Sungju Ryu, Naebeom Park, Jae-Joon Kim |
Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(1), pp. 138-146, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Ismail Gassoumi, Lamjed Touil, Bouraoui Ouni |
Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 13(4), pp. 534-543, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Dongyeob Shin, Wonseok Choi 0004, Jongsun Park 0001, Swaroop Ghosh |
Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3), pp. 520-531, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Vincent Camus, Linyan Mei, Christian C. Enz, Marian Verhelst |
Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 9(4), pp. 697-711, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Tongxin Yang, Toshinori Sato, Tomoaki Ukezono |
An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019, pp. 385-390, 2019, IEEE, 978-1-7281-3391-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Andrew Boutros, Mohamed Eldafrawy, Sadegh Yazdanshenas, Vaughn Betz |
Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2019, Seaside, CA, USA, February 24-26, 2019, pp. 94-103, 2019, ACM, 978-1-4503-6137-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Ziwei Wang, Martin A. Trefzer, Simon J. Bale, Andy M. Tyrrell |
Approximate Multiply-Accumulate Array for Convolutional Neural Networks on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2019, York, United Kingdom, July 1-3, 2019, pp. 35-42, 2019, IEEE, 978-1-7281-4770-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Vincent Camus, Christian C. Enz, Marian Verhelst |
Survey of Precision-Scalable Multiply-Accumulate Units for Neural-Network Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICAS ![In: IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019, Hsinchu, Taiwan, March 18-20, 2019, pp. 57-61, 2019, IEEE, 978-1-5386-7884-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Hao Zhang 0041, Jiongrui He, Seok-Bum Ko |
Efficient Posit Multiply-Accumulate Unit Generator for Deep Learning Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-0397-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Xinyue Zhang 0002, Yuan Wang 0001, Yawen Zhang, Jiahao Song, Zuodong Zhang, Kaili Cheng, Runsheng Wang, Ru Huang |
Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: International Conference on IC Design and Technology, ICICDT 2019, Suzhou, China, June 17-19, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1853-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Xinyue Zhang 0002, Jiahao Song, Yuan Wang 0001, Yawen Zhang, Zuodong Zhang, Runsheng Wang, Ru Huang |
An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-0735-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | M. Mohamed Asan Basiri |
Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers, pp. 247-257, 2019, Springer, 978-981-32-9766-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Dong-Ik Jeon, Kyeong-Bin Park, Ki-Seok Chung |
HMC-MAC: Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 17(1), pp. 5-8, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
34 | James Garland, David Gregg |
Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 15(3), pp. 31:1-31:24, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
34 | James Garland, David Gregg |
Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1801.10219, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
34 | Vassilis Paliouras, Konstantina Karagianni, Yann Oster |
Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018, pp. 183-190, 2018, IEEE, 978-1-5386-6365-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
34 | William Kamp, Norbert Abel, Gianni Comoretto |
Complex Multiply Accumulate Cells for the Square Kilometre Array Correlators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018, pp. 1-6, 2018, IEEE, 978-1-7281-1968-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
34 | Ahmed Saeed 0005, Kareem Mansour |
Implementation of Low-Power Multiply-Accumulate (MAC) Unit for IoT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EECS ![In: 2nd European Conference on Electrical Engineering and Computer Science, EECS 2018, Bern, Switzerland, December 20-22, 2018, pp. 356-360, 2018, IEEE, 978-1-7281-1929-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
34 | Hao Zhang 0041, Hyuk Jae Lee, Seok-Bum Ko |
Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
34 | Siam U. Hussain, Bita Darvish Rouhani, Mohammad Ghasemzadeh 0002, Farinaz Koushanfar |
MAXelerator: FPGA accelerator for privacy preserving multiply-accumulate (MAC) on cloud servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018, pp. 33:1-33:6, 2018, ACM, 978-1-5386-4114-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
34 | James Garland, David Gregg |
Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 16(2), pp. 132-135, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
34 | M. Mohamed Asan Basiri, S. K. Noor Mohammad |
Quadruple throughput fixed point quarter precision multiply accumulate circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 11(5), pp. 183-189, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
34 | James Garland, David Gregg |
Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1609.05132, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
34 | Lukas Gerlach 0001, Guillermo Payá Vayá, Holger Blume |
An area efficient real- and complex-valued multiply-accumulate SIMD unit for digital signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: 2015 IEEE Workshop on Signal Processing Systems, SiPS 2015, Hangzhou, China, October 14-16, 2015, pp. 1-6, 2015, IEEE, 978-1-4673-9604-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
34 | Rohit Kumar, Manisha Pattanaik |
A novel dual multiplier floating point multiply accumulate architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015, pp. 1-2, 2015, IEEE Computer Society, 978-1-4799-1743-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
34 | Nasibeh Nasiri, Oren Segal, Martin Margala |
Modified fused multiply-accumulate chained unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014, College Station, TX, USA, August 3-6, 2014, pp. 889-892, 2014, IEEE, 978-1-4799-4134-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
34 | Suresh Srinivasan, Ketan Bhudiya, Rajaraman Ramanarayanan, P. Sahit Babu, Tiju Jacob, Sanu Mathew, Ram Krishnamurthy 0001, Vasantha Erraguntla |
Split-Path Fused Floating Point Multiply Accumulate (FPMAC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 21st IEEE Symposium on Computer Arithmetic, ARITH 2013, Austin, TX, USA, April 7-10, 2013, pp. 17-24, 2013, IEEE Computer Society, 978-1-4673-5644-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
34 | R. Sakthivel 0002, K. Sravanthi, Harish M. Kittur |
Low power energy efficient pipelined multiply-accumulate architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2012 International Conference on Advances in Computing, Communications and Informatics, ICACCI '12, Chennai, India, August 3-5, 2012, pp. 226-231, 2012, ACM, 978-1-4503-1196-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
34 | Tobias Vejda, Johann Großschädl, Dan Page |
A Unified Multiply/Accumulate Unit for Pairing-Based Cryptography over Prime, Binary and Ternary Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, pp. 658-666, 2011, IEEE Computer Society, 978-1-4577-1048-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors |
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12), pp. 3073-3081, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
34 | Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors |
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-7, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Shanthala S., Cyril Raj, S. Y. Kulkarni |
Design and VLSI Implementation of Pipelined Multiply Accumulate Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICETET ![In: Proceedings of the Second International Conference on Emerging Trends in Engineering & Technology, ICETET 2009, Nagpur, Maharashtra, India, 16-18 December 2009, pp. 381-386, 2009, IEEE Computer Society, 978-0-7695-3884-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors |
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Annual IEEE International SoC Conference, SoCC 2009, September 9-11, 2009, Belfast, Northern Ireland, UK, Proceedings, pp. 119-122, 2009, IEEE, 978-1-4244-4940-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Fatemeh Kashfi, Sied Mehdi Fakhraie, Saeed Safari |
Designing an ultra-high-speed multiply-accumulate structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 39(12), pp. 1476-1484, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Erik Lindahl, Oscar Gustafsson |
Architecture-aware design of a decimation filter based on a dual wordlength multiply-accumulate unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSCC ![In: 42nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2008, Pacific Grove, CA, USA, October 26-29, 2008, pp. 1897-1901, 2008, IEEE, 978-1-4244-2940-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis |
Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 40(2), pp. 74-93, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | William Kamp, Andrew Bainbridge-Smith |
Multiply Accumulate Unit Optimised for Fast Dot-Product Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007, pp. 349-352, 2007, IEEE, 1-4244-1472-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Ayman A. Fayed, Walid Elgharbawy, Magdy A. Bayoumi |
A data merging technique for high-speed low-power multiply accumulate units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP (5) ![In: 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2004, Montreal, Quebec, Canada, May 17-21, 2004, pp. 145-148, 2004, IEEE, 0-7803-8484-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Johann Großschädl, Guy-Armand Kamendje |
A single-cycle (32×32+32+64)-bit multiply/accumulate unit for digital signal processing and public-key cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003, Sharjah, United Arab Emirates, December 14-17, 2003, pp. 739-742, 2003, IEEE, 0-7803-8163-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | James T. Kao, Masayuki Miyazaki, Anantha P. Chandrakasan |
A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(11), pp. 1545-1554, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Yuyun Liao, David B. Roberts |
A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(7), pp. 926-931, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | William G. Natter, Behrouz Nowrouzian |
A novel multiplier recoding technique and its application to the development of a high-speed parallel online multiply-accumulate architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 713-716, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Adimathara P. Preethy, Damu Radhakrishnan, Amos Omondi |
A high performance RNS multiply-accumulate unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001, pp. 145-148, 2001, ACM, 1-58113-351-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Dusan Suvakovic, C. André T. Salama |
A pipelined multiply-accumulate unit design for energy recovery DSP systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 16-19, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | William G. Natter, Behrouz Nowrouzian |
A novel algorithm for signed-digit online multiply-accumulate operation and its purely signed-binary hardware implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 329-332, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Adimathara P. Preethy |
High performance multiply-accumulate unit for residue number system DSP core ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2000 |
RDF |
|
34 | Christian D. Nielsen, Alain J. Martin |
Design of a delay-insensitive multiply-accumulate unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 15(3), pp. 291-311, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|