Search results for "multivoltage"

Found 11 publication records. Showing 11 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
209	Amitabh Menon, S. K. Nandy 0001, Mahesh Mehendale	Multivoltage scheduling with voltage-partitioned variable storage.	ISLPED	2003	DBLP DOI BibTeX RDF	multivoltage, high level synthesis, datapath synthesis
56	S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod	Diagnosis of Multiple-Voltage Design With Bridge Defect.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
34	Chuxiong Lin, Weifeng He, Yanan Sun 0003, Lin Shao, Bo Zhang, Jun Yang 0006, Mingoo Seok	A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
34	Jiaotong Wei, Yan Han, Ping Chen 0004	Narrow-Energy-Width CT Based on Multivoltage X-Ray Image Decomposition.	Int. J. Biomed. Imaging	2017	DBLP DOI BibTeX RDF
34	Mohamed Tagelsir Mohammadat, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin, Mark Zwolinski	Multivoltage Aware Resistive Open Fault Model.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
34	S. Saqib Khursheed, Bashir M. Al-Hashimi, Krishnendu Chakrabarty, Peter Harrod	Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
34	Qiang Ma 0002, Evangeline F. Y. Young	Multivoltage Floorplan Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
34	Xianwu Xing, Ching-Chuen Jong	Floorplan-Driven Multivoltage High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
34	Xianwu Xing, Ching-Chuen Jong	Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined Datapath.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
34	Deming Chen, Jason Cong, Junjuan Xu	Optimal simultaneous module and multivoltage assignment for low power.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Data path generation, functional unit binding, level conversion, scheduling, high-level synthesis, low power design, power optimization, multiple voltage
28	Ashish Srivastava, Dennis Sylvester	Minimizing total power by simultaneous Vdd/Vth assignment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF