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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
30 | Sheetanshu L. Pandey, Kothanda R. Subramanian, Philip A. Wilsey |
A Semantic Model of VHDL for Validating Rewriting Algebras. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 167-176, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
rewriting algebras validation, declarative style, process-folding, CAD tool optimization, VHDL, formal model, semantic model, hardware description languages, interval temporal logic, dynamic semantics |
9 | Sheetanshu L. Pandey, Kothanda Umamageswaran, Philip A. Wilsey |
VHDL semantics and validating transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7), pp. 936-955, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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