Search results for "radix-4"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
106	Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli	Digit-Recurrence Dividers with Reduced Logical Depth.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Digit-by-digit division, algorithms and architectures for computer arithmetic, division radix 4, division radix 16
82	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	Improved radix-4 and radix-8 FFT algorithms.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
81	Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera	Radix-4 Vectoring Cordic Algorithm And Architectures.	ASAP	1996	DBLP DOI BibTeX RDF	radix-4 vectoring CORDIC algorithm, radix-4 vectoring CORDIC architectures, vectoring mode, microrotations, zero skipping technique, recursive architectures, matrix triangularization, rotation angle, computational complexity, complexity, parallel architectures, singular value decomposition, SVD, signal processing, digital arithmetic, digital arithmetic, matrix algebra, pipelined architectures
77	Alberto Nannarelli, Tomás Lang	Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
77	Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera	Radix-4 Vectoring CORDIC Algorithm and Architectures.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
73	Alberto Nannarelli, Tomás Lang	Power-delay tradeoffs for radix-4 and radix-8 dividers.	ISLPED	1998	DBLP DOI BibTeX RDF
72	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	A New Family of High.Performance Parallel Decimal Multipliers.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
72	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	A split-radix algorithm for 2-D DFT.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
63	Jin-Hua Hong, Cheng-Wen Wu	Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
63	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	An efficient split-radix FFT algorithm.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
63	Belle W. Y. Wei, He Du, Honglu Chen	A complex-number multiplier using radix-4 digits.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	complex-number multiplier, radix-4 digits, arithmetic datapath, complex-number digital signal processor, binary signed digits, fast multiplication, compact layout, three-multiplication scheme, radix-4 operands, delays, delay, encoding, digital arithmetic, multiplying circuits, binary additions, coding scheme
61	Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, Nicolas Vaucher	Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers.	VLSI Design	1995	DBLP DOI BibTeX RDF	layout synthesis, radix-2 dividers, pseudo-radix-4 dividers, redundant number notation, carry-propagation-free addition/subtraction, VLSI, logic CAD, circuit layout CAD, CMOS logic circuits, VLSI implementation, integrated circuit layout, redundant number systems, dividing circuits, digit-recurrence division
54	David W. Matula, Alex Fit-Florea	Prescaled Integer Division.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
54	David L. Harris, Stuart F. Oberman, Mark Horowitz	SRT Division Architectures and Implementations.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	skew-tolerant, Computer arithmetic, floating point units, SRT division, domino circuits
50	Xin Xiao, Erdal Oruklu, Jafar Saniie	Fast memory addressing scheme for radix-4 FFT implementation.	EIT	2009	DBLP DOI BibTeX RDF
50	Satyendra R. Datla, Mitchell A. Thornton, David W. Matula	A Low Power High Performance Radix-4 Approximate Squaring Circuit.	ASAP	2009	DBLP DOI BibTeX RDF
47	Attif A. Ibrahem, Hamed Elsimary, Aly E. Salama	FPGA Implementation of Fast Radix 4 Division Algorithm.	IWSOC	2004	DBLP DOI BibTeX RDF	fast division, radix 4 division, quotient selection, Field programmable gate arrays (FPGAs)
47	Jen-Shiun Chiang, Min-Shiou Tsai	A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	floating-point division, new Svoboda-Tung division, radix-4, Svoboda-Tung division, computer arithmetic, prescaling, signed digit number system
45	Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van	Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
45	Elisardo Antelo, Tomás Lang, Javier D. Bruguera	Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Very-high radix algorithms, selection by rounding, angle and modulus calculation, rotation, CORDIC
45	Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi 0001	High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables.	ISMVL	2000	DBLP DOI BibTeX RDF	Quotient digit selection tables, High-radix division, VLSI, Computer arithmetic, Signed-digit number systems, SRT division
45	Javier D. Bruguera, Nicolás Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata	Cordic based parallel/pipelined architecture for the Hough transform.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
45	Luis A. Montalvo, Alain Guyot	Svoboda-Tung division with no compensation.	VLSI Design	1995	DBLP DOI BibTeX RDF	Svoboda-Tung division, radix-b division algorithm, iteration overflow, most significant digits, radix-b algorithm, IEEE normalised divisor, pre-scaling technique, stepwise approximation, VLSI, iterative methods, digital arithmetic, VLSI implementation, prescalers, dividing circuits
43	T. C. Choinski, T. T. Tylaska	Generation of Digit Reversed Address Sequences for Fast Fourier Transforms.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	digit reversed address sequences generation, radix-4, binary counter, address sequences, fast Fourier transforms, fast Fourier transforms, hardware design, computerised signal processing, radix-2
41	Johann Großschädl	A unified radix-4 partial product generator for integers and binary polynomials.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
38	Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou	A high-speed radix-4 multiplexer-based array multiplier.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	modified booth, multiplexer-based, radix-4 multiplier, array multiplier
36	Seungbeom Lee, Sin-Chong Park	Modified SDF Architecture for Mixed DIF/DIT FFT.	ISCAS	2007	DBLP DOI BibTeX RDF
36	Rui Deng, Yujie Zhou	Improvement to Montgomery Modular Inverse Algorithm.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Montgomery modular inverse, cryptography, modular arithmetic
36	Cor Meenderinck, Sorin Cotofana	Electron counting based high-radix multiplication in single electron tunneling technology.	ISCAS	2006	DBLP DOI BibTeX RDF
36	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	Design of a multidimensional split vector-radix decimation-in-frequency FFT algorithm.	ISCAS	2006	DBLP DOI BibTeX RDF
36	Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis	A reusable IP FFT core for DSP applications.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
36	Behrooz Parhami	Tight Upper Bounds on the Minimum Precision Required of the Divisor and the Partial Remainder in High-Radix Division.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	digit-selector PLA, high-radix division, p-d plot, quotient digit selection, SRT division, Digit-recurrence division
36	Jaehyun Baek, Byung S. Son, Byung G. Jo, Myung Hoon Sunwoo, Seung Keun Oh	A continuous flow mixed-radix FFT architecture with an in-place algorithm.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
36	Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata	Redundant CORDIC Rotator Based on Parallel Prediction.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	High speed processor, Parallel prediction, Parallel architecture, CORDIC algorithm, Redundant arithmetic
32	Nathaniel Ross Pinckney, David Money Harris	Parallelized radix-4 scalable montgomery multipliers.	SBCCI	2007	DBLP DOI BibTeX RDF	cryptography, RSA, Montgomery Multiplication
32	Tung N. Pham, Earl E. Swartzlander Jr.	Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology.	ASAP	2006	DBLP DOI BibTeX RDF
32	Jin-Hua Hong, Bin-Yan Tsai	A Fast Bit-Interleaving RSA Cryptosystem Based on Radix-4 Cellular-Array Modular Multiplier.	APCCAS	2006	DBLP DOI BibTeX RDF
32	Ayman M. El-Khashab, Earl E. Swartzlander Jr.	An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform.	ASAP	2003	DBLP DOI BibTeX RDF
32	A. Perez-Pascual, T. Sansaloni, Javier Valls	FPGA-based radix-4 butterflies for HIPERLAN/2.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
32	Alberto Nannarelli, Tomás Lang	Low-Power Radix-4 Combined Division and Square Root.	ICCD	1999	DBLP DOI BibTeX RDF
32	C.-C. Wang, C. J. Huang, G.-C. Lin	A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
29	V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, Jonathan J. Ashley, Razmik Karabed	A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder.	ASAP	2000	DBLP DOI BibTeX RDF	disk-drive read channels, high-speed Viterbi decoder, radix-4 add-compare-select, bit-level pipelining, full-custom macros, datapath generator assisted design, 0.25 micron, 550 MHz, CMOS technology, redundant number representations
29	Naofumi Takagi	A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	division subtraction, radix-4 modular multiplication hardware algorithm, residue calculation, repeated multiply-add, serial-parallel modular multiplier, cellular array structure, VLSI, cryptography, digital arithmetic, public-key cryptosystems, modular exponentiation, RSA cryptosystem, redundant representation, bit slice
29	Milos D. Ercegovac, Tomás Lang	Radix-4 Square Root Without Initial PLA.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	redundant result, on-the-fly rounding, radix-4 square-root algorithm, redundant residual, on-the-fly conversion, result-digit selection, digital arithmetic, division, number theory, logic arrays
28	Ramalakshmi Barma Venkata, Noorbasha Fazal	FPGA Implementation of Optimized Radix 4 and Radix 8 Booth Algorithm.	Int. J. Perform. Eng.	2021	DBLP DOI BibTeX RDF
28	Sirani M. Perera, Daniel Silverio, Austin Ogle	Efficient Split-Radix and Radix-4 DCT Algorithms and Applications.	SEA²	2019	DBLP DOI BibTeX RDF
28	Renato H. Neuenfeld, Mateus Beck Fonseca, Eduardo A. C. da Costa, Jean P. Oses	Exploiting addition schemes for the improvement of optimized radix-2 and radix-4 fft butterflies.	LASCAS	2017	DBLP DOI BibTeX RDF
28	Renato Neuenfeld, Mateus Fonseca, Eduardo A. C. da Costa	Design of optimized radix-2 and radix-4 butterflies from FFT with decimation in time.	LASCAS	2016	DBLP DOI BibTeX RDF
28	Khalid Javeed, Xiaojun Wang 0001	Radix-4 and radix-8 booth encoded interleaved modular multipliers over general Fp.	FPL	2014	DBLP DOI BibTeX RDF
28	Ramya Muralidharan, Chip-Hong Chang	Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
28	Sian-Jheng Lin, Wei-Ho Chung	The split-radix fast Fourier transforms with radix-4 butterfly units.	APSIPA	2013	DBLP DOI BibTeX RDF
28	Andrew Carter, Paula Ning, William Koven, David Money Harris, Michael Braly, Nathan Jones, Julien Massas, Trevin Murakami, Alexandra Simoni, Sanu Mathew	Comparison of parallelized radix-2 and radix-4 scalable Montgomery multipliers.	ACSSC	2013	DBLP DOI BibTeX RDF
28	Waqar Hussain 0001, Fabio Garzia, Jari Nurmi	Evaluation of Radix-2 and Radix-4 FFT processing on a reconfigurable platform.	DDECS	2010	DBLP DOI BibTeX RDF
28	Chitlur Nagabhushan, Olga Kosheleva, Sergio D. Cabrera, Glenn A. Gibson	Design of Radix-2 and Radix-4 FFT Processors Using a Modular Architecture Family.	PDPTA	1996	DBLP BibTeX RDF
28	Jan Fandrianto	Algorithm for high speed shared radix 4 division and radix 4 square-root.	IEEE Symposium on Computer Arithmetic	1987	DBLP DOI BibTeX RDF
27	Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi	An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm.	Public Key Cryptography	2008	DBLP DOI BibTeX RDF	MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication
27	Zhongfeng Wang 0001	High-Speed Recursion Architectures for MAP-Based Turbo Decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
27	Zhongjun Wang, Lee Guek Yeo, Wenzhen Li, Yanxin Yan, Yujing Ting, Masayuki Tomisawa	A Novel FFT Processor for OFDM UWB Systems.	APCCAS	2006	DBLP DOI BibTeX RDF
27	José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera	High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	digit-recurrence, high-radix, selection by rounding, computer arithmetic, logarithm
27	Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	A New Pipelined Array Architecture for Signed Multiplication.	SBCCI	2003	DBLP DOI BibTeX RDF
27	Tim Courtney, Richard H. Turner, Roger F. Woods	Multiplexer Based Reconfiguration for Virtex Multipliers.	FPL	2000	DBLP DOI BibTeX RDF
27	Francisco Argüello, Emilio L. Zapata	Constant geometry split-radix algorithms.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
27	Chung Nan Lyu, David W. Matula	Redundant Binary Booth Recoding.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF
27	Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata	Digit On-line Large Radix CORDIC Rotator.	ASAP	1995	DBLP DOI BibTeX RDF	Digit on-line processing, Pipelined array architecture, VLSI architecture, Application-specific processor, CORDIC algorithm
27	Paolo Montuschi, Luigi Ciminiera	Radix-8 division with over-redundant digit set.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
27	Stephen E. McQuillan, John V. McCanny	Fast VLSI algorithms for division and square root.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
23	Ismo Hänninen, Jarmo Takala	Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata.	SAMOS	2009	DBLP DOI BibTeX RDF	nanotechnology, multiplication, arithmetic, QCA
23	Pouya Dormiani, Milos D. Ercegovac, Jean-Michel Muller	Design and Implementation of a Radix-4 Complex Division Unit with Prescaling.	ASAP	2009	DBLP DOI BibTeX RDF
23	Seung Ho Ok, Byung In Moon	A Digit Reversal Circuit for the Variable-Length Radix-4 FFT.	FGCN (2)	2007	DBLP DOI BibTeX RDF
23	Bonseok Koo, Dongwook Lee, Gwonho Ryu, Taejoo Chang, Sangjin Lee 0002	High-Speed RSA Crypto-processor with Radix-4 Modular Multiplication and Chinese Remainder Theorem.	ICISC	2006	DBLP DOI BibTeX RDF	Booth’s algorithm, RSA, Chinese Remainder Theorem, Montgomery multiplication, Carry Save Adder
23	Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro 0001, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis	A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
23	Justin Hensley, Anselmo Lastra, Montek Singh	A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier.	ASYNC	2005	DBLP DOI BibTeX RDF
23	Tomás Lang, Elisardo Antelo	Radix-4 Reciprocal Square-Root and Its Combination with Division and Square Root.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Combined division, reciprocal square root, exact rounding, staircase selection function, square root, digit-recurrence algorithm
23	Yi Yang, Chunyan Wang 0004, M. Omair Ahmad, M. N. S. Swamy	An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT core.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
23	Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli	Fast Radix-4 Retimed Division with Selection by Comparisons.	ASAP	2002	DBLP DOI BibTeX RDF
23	Tomás Lang, Elisardo Antelo	Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
18	Haijun Li, Hongbo Zou, Peirong Ji, Xuejun Zhou	An Algorithm for Computing 4^M-Point DFT Based on 4-Point DFT Block.	ICYCS	2008	DBLP DOI BibTeX RDF
18	Soo-Chang Pei, Kuo-Wei Chang	Efficient Bit and Digital Reversal Algorithm Using Vector Calculation.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
18	Teemu Pitkänen, Tero Partanen, Jarmo Takala	Low-Power Twiddle Factor Unit for FFT Computation.	SAMOS	2007	DBLP DOI BibTeX RDF
18	Abdulah Abdulah Zadeh	High Speed Modular Divider Based on GCD Algorithm.	ICICS	2007	DBLP DOI BibTeX RDF	GCD algorithm, Radix four, Finite Field, ECC
18	Chih-Peng Fan, Guo-An Su	A Grouped Fast Fourier Transform Algorithm Design For Selective Transformed Outputs.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Peter Kornerup	Digit Selection for SRT Division and Square Root.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Digit selection, division, square root
18	Marcelo E. Kaihara, Naofumi Takagi	A Hardware Algorithm for Modular Multiplication/Division.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	modular division, cryptography, Computer arithmetic, modular multiplication, redundant representation, hardware algorithm
18	David Guevorkian, Petri Liuha, Aki Launiainen, Konsta Punkka, Ville Lappalainen	A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms.	SAMOS	2005	DBLP DOI BibTeX RDF
18	Alessandro Cilardo, Antonino Mazzeo, Nicola Mazzocca, Luigi Romano	A Novel Unified Architecture for Public-Key Cryptography.	DATE	2005	DBLP DOI BibTeX RDF
18	Jun-Hong Chen, Ming-Der Shieh, Chien-Ming Wu	Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
18	Li-Hsun Chen, Oscal T.-C. Chen	A hardware-efficient FIR architecture with input-data and tap folding.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
18	Yijun Liu, Stephen B. Furber	The design of a low power asynchronous multiplier.	ISLPED	2004	DBLP DOI BibTeX RDF	Booth's algorithm, low power, benchmark, multiplier, asynchronous logic
18	Mohd. Hasan, Tughrul Arslan	A triple port RAM based low power commutator architecture for a pipelined FFT processor.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
18	Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	A New Architecture for Signed Radix-2m Pure Array Multipliers.	ICCD	2002	DBLP DOI BibTeX RDF
18	Elisardo Antelo, Tomás Lang, Javier D. Bruguera	Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
18	Harald Rueß, Natarajan Shankar, Mandayam K. Srivas	Modular Verification of SRT Division.	CAV	1996	DBLP DOI BibTeX RDF
18	John S. Fernando, Milos D. Ercegovac	Conventional and on-line arithmetic designs for high-speed recursive digital filters.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
18	Paolo Montuschi, Luigi Ciminiera	n × n carry-save multipliers without final addition.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
15	Mahn-ling Woo, Rosemary A. Renaut	Unordered parallel distance-1 and distance-2 FFT algorithms of radix 2 and (4-2).	SAC	1994	DBLP DOI BibTeX RDF	mixed-radix (4-2) FFT, parallel FFT algorithms, radix-2 FFT, complexity analysis
15	Marcel Lapointe, Huu Tuê Huynh, Paul Fortier	Systematic Design of Pipelined Recursive Filters.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	systematic design, pipelined recursive filters, multiplication algorithm, most significant digit first, pipelining delays, minimum hardware, minimum latency, number system radix, second-order all-pole filter, radix-4 representation, delays, digital arithmetic, pipeline processing, multiplier, digital filters
15	Jeong-A Lee, Tomás Lang	Constant-Factor Redundant CORDIC for Angle Calculation and Rotation.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	rotation direction, angle calculation, constant-factor redundant-CORDIC, plane rotations, correcting iterations, radix-4, convergence, iterative methods, digital arithmetic, number theory, convergence of numerical methods, algorithm theory, scale factor, radix-2
15	Milos D. Ercegovac, Tomás Lang	Fast Multiplication Without Carry-Propagate Addition.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	fast multiplication, carry-propagate adder, LRCF scheme, general radix r, radix-4 signed-digit implementation, digital arithmetic
15	Luigi Ciminiera, Paolo Montuschi	Higher Radix Square Rooting.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	nonrestoring square root algorithms, feasible algorithms, digit set, radicand bits, starting value, partial remainder bits, digit selection, radix 4, carry-save, constraints, representation, digital arithmetic, bounds, number theory, radix
15	Tich T. Dao, Edward J. McCluskey, Lewis K. Russel	Multivalued Integrated Injection Logic.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Multilevel I2L, Post logic, quaternary logic, quaternary ROM, quaternary flip-flops, radix-4 arithmetic, threshold I2L, multivalued logic