Search results for "reconfigurable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
77	Lars Bauer, Muhammad Shafique 0001, Jörg Henkel	MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	extensible embedded processor, reconfigurable computing, kernel, accelerator, replacement, run-time adaptation
66	Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen	Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	heterogeneous reconfigurable multimedia systems, energy efficiency, reconfigurable computing, discrete wavelet transform, lifting scheme
63	Fengbin Qi, Xianyi Zhang, Shanshan Wang, Xingquan Mao	RCC: A New Programming Language for Reconfigurable Computing.	HPCC	2009	DBLP DOI BibTeX RDF
63	Ronald Scrofano, Viktor K. Prasanna	A Performance model for accelerating scientific applications on reconfigurable computers.	FPGA	2006	DBLP DOI BibTeX RDF
61	Mahmood Fazlali, Mohammad K. Fallah, Mahdy Zolghadr, Ali Zakerolhosseini	A New Datapath Merging Method for Reconfigurable System.	ARC	2009	DBLP DOI BibTeX RDF	Datapath Merging, Maximum Weighted Clique Algorithm, High Level Synthesis, Reconfigurable Computing
54	Mounir Hamdi, J. Tong, C. W. Kin	Fast sorting algorithms on reconfigurable array of processors with optical buses.	ICPADS	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, optical buses, parallel algorithms, parallel architectures, sorting, reconfigurable architectures, optical interconnections, system buses, sorting algorithms, reconfigurable array, reconfigurable arrays, parallel sorting algorithm
54	Katherine Compton, Scott Hauck	Reconfigurable computing: a survey of systems and software.	ACM Comput. Surv.	2002	DBLP DOI BibTeX RDF	field-programmable, manual design, FPGA, reconfigurable computing, reconfigurable architectures, reconfigurable systems, Automatic design
54	Francisco Barat, Rudy Lauwereins	Reconfigurable Instruction Set Processors: A Survey.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	dynamically reconfigurable instruction set processor, reconfigurable functional unit, application specific instructions, reconfigurable computing
54	Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi	CODA-R: a reconfigurable testbed for real-time parallel computation.	RTCSA	1997	DBLP DOI BibTeX RDF	CODA-R, reconfigurable testbed, real-time parallel computation, reconfigurable field programmable gate arrays, total execution time, prototype reconfigurable real-time parallel system, real-time parallel architecture, field programmable gate arrays, real-time system, processing elements, computing engine
54	Francisco Barat, Rudy Lauwereins, Geert Deconinck	Reconfigurable Instruction Set Processors from a Hardware/Software Perspective.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	Reconfigurable instruction set processor overview, compiler, microprocessor, reconfigurable logic
54	Ronald Scrofano, Maya B. Gokhale, Frans Trouw, Viktor K. Prasanna	Accelerating Molecular Dynamics Simulations with Reconfigurable Computers.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF	Physics, Reconfigurable hardware, Distributed architectures, Chemistry
54	Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich	Task scheduling for heterogeneous reconfigurable computers.	SBCCI	2004	DBLP DOI BibTeX RDF	hardware preemption, scheduling, FPGA, placement, reconfigurable computing, partial reconfiguration
50	Pao-Ann Hsiung, Chao-Sheng Lin, Chih-Feng Liao	Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	scheduling, performance evaluation, partitioning, placement, design-space exploration, Reconfigurable systems
49	Kang Sun, Jun Zheng, Yuanyuan Li, Xuezeng Pan	Design of a Simulator for Mesh-Based Reconfigurable Architectures.	NPC	2007	DBLP DOI BibTeX RDF	simulator, reconfigurable computing, dynamic reconfiguration, reconfigurable mesh
49	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Partitioning Methodology for Heterogeneous Reconfigurable Functional Units.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	heterogeneous reconfigurable architectures, coarse-grain reconfigurable hardware, scheduling, FPGA, partitioning, performance improvements
49	Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein	Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Term Rewriting Systems (TRS), algebraic manipulation, dynamically reconfigurable systems, Fast Fourier Transform (FFT), reconfigurable computing, systolic arrays, rewriting-logic
49	Ali Akoglu, Aravind Dasu, Arvind Sudarsanam, Mayur Srinivasan, Sethuraman Panchanathan	Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing.	IPDPS	2002	DBLP DOI BibTeX RDF	reconfigurable media processor, recurring pattern analyzer, mobile multimedia processing, partition, dynamic reconfiguration, reconfigurable architectures, data flow graph, control flow graph, MPEG4, hardware software co-design, hardware software partitioning, routing architecture
49	Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, Eliseu M. Chaves Filho	MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	reconfigurable cell array, bit-correlation, dynamic reconfiguration, Single Instruction Multiple Data, multimedia applications, video compression, MPEG-2, Reconfigurable systems, data encryption, target recognition
49	Jinguo Liu, Yuechao Wang, Bin Li 0001, Shugen Ma, Dalong Tan	Center-configuration selection technique for the reconfigurable modular robot.	Sci. China Ser. F Inf. Sci.	2007	DBLP DOI BibTeX RDF	center-configuration, configuration network, reconfiguration cost matrix, center-configuration coefficient, modular robot, reconfigurable robot
49	Giovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto	A Data Oriented Approach to the Design of Reconfigurable Stream Decoders.	ESTIMedia	2005	DBLP DOI BibTeX RDF
47	Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter	A reconfigurable unit for a clustered programmable-reconfigurable processor.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, technology scaling, reconfigurable processor
45	Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	The Molen compiler for reconfigurable processors.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	FPGA, reconfigurable computing, Instruction scheduling
45	I-Hsuan Huang, Chih-Chun Wang, Shih-Min Chu, Cheng-Zen Yang	Function-Level Multitasking Interface Design in an Embedded Operating System with Reconfigurable Hardware.	EUC	2007	DBLP DOI BibTeX RDF	hardware function, FPGA-based computer, ?C/OS, Reconfigurable computing, multitasking
45	Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011	Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Data communications devices, application studies resulting in better multiple-processor systems, reconfigurable hardware, wireless systems, special-purpose and application-based systems, adaptable architectures, heterogeneous (hybrid) systems, design studies, signal processing systems
45	Nicolas Ventroux, Stéphane Chevobbe, Frédéric Blanc 0001, Thierry Collette	An Auto-adaptative Reconfigurable Architecture for the Control.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF	adaptative reconfigurable architecture, control parallelism, dynamic reconfiguration
45	Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck	Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	coarse grained logic, code generation, software pipelining, vliw, reconfigurable processor, spatial computation
45	Alan A. Bertossi, Alessandro Mei	A Residue Number System on Reconfigurable Mesh with Applications to Prefix Sums and Approximate String Matching.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	string matching with $k$ mismatches, VLSI, residue number system, reconfigurable mesh, prefix sums, Number representation
44	Jochen Strunk, Toni Volkmer, Klaus Stephan, Wolfgang Rehm, Heiko Schick	Impact of run-time reconfiguration on design and speed - A case study based on a grid of run-time reconfigurable modules inside a FPGA.	IPDPS	2009	DBLP DOI BibTeX RDF
44	Li-Hsun Chen, Oscal T.-C. Chen, Ruey-Ling Ma	A high-efficiency reconfigurable digital signal processor for multimedia computing.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
41	Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow	A Desktop Computer with a Reconfigurable Pentium®.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Pentium®, simulator, model, FPGA, architecture, operating system, reconfigurable, emulator, exploration, accelerator, processor
40	Saad AlKasabi, Salim Hariri	Performance analysis of a high-speed dynamically reconfigurable LAN.	LCN	1995	DBLP DOI BibTeX RDF	dynamically reconfigurable LAN, reconfigurable switch, highspeed multi-link ring local area network, switch reconfigurability, multi-link ring network, M/M/n, M/D/n, virtual channel occupancy probabilities, infinite state Markov model, finite state Markov model, OPNET tool, packet transfer time, virtual channel flow, performance evaluation, field programmable gate arrays, performance analysis, local area networks, reconfigurable architectures, wormhole routing, network performance, queuing systems, interconnection topologies, system throughput
40	Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis	Compiler assisted architectural exploration for coarse grained reconfigurable arrays.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	coarse-grained reconfigurable arrays, reconfigurable computing, modulo scheduling, architectural exploration
40	David R. Martinez, Tyler J. Moeller, Ken Teitelbaum	Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	VLSI rader signal processor, front end high performance filtering, digital filtering mapped to reconfigurable computing, commercial FPGA hardware, reconfigurable hardware
40	Akihiro Matsuura, Akira Nagoya	Summation Algorithms on Constrained Reconfigurable Meshes.	ISPAN	1999	DBLP DOI BibTeX RDF	constrained reconfigurable mesh, Bit summation, parallel algorithm, reconfigurable mesh
40	Koji Nakano, Stephan Olariu	An Efficient Algorithm for Row Minima Computations on Basic Reconfigurable Meshes.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	Monotone matrices, totally monotone matrices, row minima, basic reconfigurable meshes, cellular system design, VLSI design, search problems, reconfigurable meshes, facility location problems
40	Lizyamma Kurian, Daniel Brewer, Eugene John	Design of a highly reconfigurable interconnect for array processors.	VLSI Design	1995	DBLP DOI BibTeX RDF	reconfigurable interconnect, static-RAM programming technology, faulty elements, fault-tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, network topology, reconfigurable architectures, array processors, interconnection topologies, mesh topologies
40	Kuen-Cheng Chiang, Zhi-Wei Chen, Jean Jyh-Jiun Shann	Design and implementation of a reconfigurable hardware for secure embedded systems.	AsiaCCS	2006	DBLP DOI BibTeX RDF	secured embedded system, AES, RSA, reconfigurable architecture, DES, processing element
40	Ronald Scrofano, Viktor K. Prasanna	Molecular dynamics - Preliminary investigation of advanced electrostatics in molecular dynamics on reconfigurable computers.	SC	2006	DBLP DOI BibTeX RDF	FPGA, reconfigurable, molecular dynamics, electrostatics
40	Russell Tessier, Wayne P. Burleson	Reconfigurable Computing for Digital Signal Processing: A Survey.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	FPGA, survey, reconfigurable computing, signal processing
40	Venkatavasu Bokka, Himabindu Gurla, Stephan Olariu, James L. Schwing	Constant-Time Algorithms for Constrained Triangulations on Reconfigurable Meshes.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	Computer-aided manufacturing, constrained triangulations, constant time algorithms, robotics, CAD, VLSI design, reconfigurable meshes, computer-aided geometric design
40	Tatsuya Hayashi, Koji Nakano, Stephan Olariu	An O((log log n)2) Time Algorithm to Compute the Convex Hull of Sorted Points on Reconfigurable Meshes.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	pattern recognition, mobile computing, image processing, Convex hulls, morphology, reconfigurable meshes
40	Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
40	Wesley Peck, Erik K. Anderson, Jason Agron, Jim Stevens, Fabrice Baijot, David Andrews 0001	Hthreads: A Computational Model for Reconfigurable Devices.	FPL	2006	DBLP DOI BibTeX RDF
40	Wenyin Fu, Katherine Compton	A Simulation Platform for Reconfigurable Computing Research.	FPL	2006	DBLP DOI BibTeX RDF
40	Wenyin Fu, Katherine Compton	An Execution Environment for Reconfigurable Computing.	FCCM	2005	DBLP DOI BibTeX RDF
40	Christian Haubelt	Design Space Exploration for Distributed Hardware Reconfigurable Systems.	FPL	2004	DBLP DOI BibTeX RDF
38	Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger	A Synthesis System For Bus-Based Wavefront Array Architectures.	ASAP	1996	DBLP DOI BibTeX RDF	synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations
37	Vikas Aggarwal, Alan D. George, Kishore Yalamanchili, Changil Yoon, Herman Lam, Greg Stitt	Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+.	HPRCTA@SC	2009	DBLP DOI BibTeX RDF	parallel programming, programming language, reconfigurable computing, productivity, portability, programming model
37	Katarzyna Leijten-Nowak, Jef L. van Meerbergen	Embedded Reconfigurable Logic Core for DSP Applications.	FPL	2002	DBLP DOI BibTeX RDF
37	Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon	Stream Computations Organized for Reconfigurable Execution (SCORE).	FPL	2000	DBLP DOI BibTeX RDF
37	David Robinson, Patrick Lysaght	Verification of Dynamically Reconfigurable Logic.	FPL	2000	DBLP DOI BibTeX RDF
36	Esam El-Araby, Iván González 0004, Tarek A. El-Ghazawi	Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	field programmable gate arrays (FPGA), High performance computing, reconfigurable computing, dynamic partial reconfiguration
35	Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab	Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches.	ASP-DAC	2007	DBLP DOI BibTeX RDF	reconfigurable instant-on system, ultralow-power reconfigurable computing, complementary nanoelectromechanical carbon nanotube switches, coplanar carbon nanotubes, low operation voltages, built-in energy storage, CNEMS, stable on-off state, latching mechanism, nonvolatile memory-mode operation, CMOS transistors, system development, leakage current
35	Grigoris Dimitroulakos, Michalis D. Galanis, Nikos Kostaras, Costas E. Goutis	A unified evaluation framework for coarse grained reconfigurable array architectures.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	coarse-grained reconfigurable arrays, reconfigurable romputing, Modulo scheduling, architectural exploration
35	Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo	The design of dynamically reconfigurable datapath coprocessors.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	coarse-grain reconfigurable fabric, reconfigurable datapath, Loop pipelining, interconnection design, datapath synthesis
35	Hossam A. ElGindy, Lachlan Wetherall	A simple Voronoi diagram algorithm for a reconfigurable mesh.	IPPS	1995	DBLP DOI BibTeX RDF	Voronoi diagram algorithm, planar points, worst case running, communication diameter, scheduling, load balancing, computational geometry, reconfigurable architectures, reconfigurable mesh
35	Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, Thomas Wild	Reconfigurable Processing Units vs. Reconfigurable Interconnects.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
35	Minghui Wang, Shugen Ma, Bin Li 0001, Yuechao Wang	Configuration representation and reconfiguration optimization for the reconfigurable robots with independent manipulation.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	reconfigurable robots with independent manipulation, configuration representation, reconfiguration optimization
35	Like Yan, Gang Wang, Tianzhou Chen	The input-aware dynamic adaptation of area and performance for reconfigurable accelerator.	FPGA	2009	DBLP DOI BibTeX RDF	dynamic adaption, reconfigurable system, loop unrolling, loop accelerator
35	Jinguo Liu, Shugen Ma, Yuechao Wang, Bin Li 0001	Network-based reconfiguration routes for a self-reconfigurable robot.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	reconfiguration route, network-based reconfiguration, configuration network, modular robot, self-reconfigurable robot
35	Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi	Compiling custom instructions onto expression-grained reconfigurable architectures.	CASES	2008	DBLP DOI BibTeX RDF	horizontal microprogramming, compilers, instruction set extensions, coarse-grained reconfigurable architectures, data-flow architectures
35	Valeri Kirischian, Vadim Geurkov, Lev Kirischian	A multi-mode video-stream processor with cyclically reconfigurable architecture.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	cost-performance ratio, video-stream processor, FPGA, computer architecture, reconfigurable computing, dynamic reconfiguration, pre-fetching, temporal partitioning
35	Ling Zhuo, Viktor K. Prasanna	Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Reconfigurable Computing Systems.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	computations on matrices, field-programmable gate arrays, parallel algorithms, Scientific computing, reconfigurable hardware
35	Mary Mehrnoosh Eshaghian-Wilner, Alexander Khitun, Shiva Navab, Kang L. Wang	The spin-wave nanoscale reconfigurable mesh and the labeling problem.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	nanoscale architectures, image processing, reconfigurable mesh, Spin waves
35	Esben Hallundbæk Østergaard, Kristian Kassow, Richard A. Beck, Henrik Hautop Lund	Design of the ATRON lattice-based self-reconfigurable robot.	Auton. Robots	2006	DBLP DOI BibTeX RDF	Design, Robotics, Morphology, Mechanics, Self-reconfigurable
35	Wei Xu, Shigang Wang, An-Lin Wang, Guobao Wang	Towards an Efficient Self-organizing Reconfiguration Method for Self-reconfigurable Robots.	J. Intell. Robotic Syst.	2003	DBLP DOI BibTeX RDF	descriptive model, metamorphic rules, self-organizing, modular robots, self-reconfigurable robots
35	Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka	Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	SRAM test, SRAM-based reconfigurable cell, memory tester, marching test
35	Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh, Tobias G. Noll	Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	heterogeneous reconfigurable systems, dedicated ASICs, coprocessor board, CardBus, multimedia applications, text search
35	Venkatavasu Bokka, Koji Nakano, Stephan Olariu, James L. Schwing, Larry Wilson	Optimal Algorithms for the Multiple Query Problem on Reconfigurable Meshes, with Applications.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	pattern recognition, parallel algorithms, image processing, robotics, Query processing, computational geometry, database design, morphology, reconfigurable mesh
35	Alan A. Bertossi, Alessandro Mei	Constant Time Dynamic Programming on Directed Reconfigurable Networks.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	directed links, VLSI, dynamic programming, shortest paths, Reconfigurable architectures, longest common subsequence
35	Ronald D. Williams, Brian D. Kuebert	Reconfigurable Pipelines in VLIW Execution Units.	FCCM	1999	DBLP DOI BibTeX RDF	very long instruction word, pipelines, reconfigurable computing
35	Stephan Olariu, James L. Schwing, Jingyuan Zhang	Efficient Image Computations on Reconfigurable Meshes.	CONPAR	1992	DBLP DOI BibTeX RDF	bus systems, computer vision, image processing, segmentation, robotics, convex hull, reconfigurable meshes, area, perimeter, component labeling
35	Daniele Piazza, John Kountouriotis, Michele d'Amico, Kapil R. Dandekar	A technique for antenna configuration selection for reconfigurable circular patch arrays.	IEEE Trans. Wirel. Commun.	2009	DBLP DOI BibTeX RDF
35	Alfred Grau, Hamid Jafarkhani, Franco De Flaviis	A reconfigurable multiple-input multiple-output communication system.	IEEE Trans. Wirel. Commun.	2008	DBLP DOI BibTeX RDF
35	Guy Gogniat, Tilman Wolf, Wayne P. Burleson, Jean-Philippe Diguet, Lilian Bossuet, Romain Vaslin	Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
35	Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro	Balancing reconfigurable data path resources according to application requirements.	IPDPS	2008	DBLP DOI BibTeX RDF
35	Kehuai Wu, Jan Madsen	COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems.	ICSAMOS	2007	DBLP DOI BibTeX RDF
35	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform.	PATMOS	2007	DBLP DOI BibTeX RDF
35	Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis	Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic.	IPDPS	2006	DBLP DOI BibTeX RDF
35	Ronald Scrofano, Maya B. Gokhale, Frans Trouw, Viktor K. Prasanna	Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers.	FCCM	2006	DBLP DOI BibTeX RDF
35	Yeong-Kang Lai, Lien-Fei Chen, Jian-Chou Chen, Chun-Wei Chiu	A two-way SIMD-based reconfigurable computing architecture for multimedia applications.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
35	Jonathan E. Luntz, James R. Moyne, Dawn M. Tilbury	On-line control reconfiguration at the machine and cell levels: case studies from the reconfigurable factory testbed.	ETFA	2005	DBLP DOI BibTeX RDF
35	Jens Braunes, Steffen Köhler, Rainer G. Spallek	RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures.	ARCS	2004	DBLP DOI BibTeX RDF
35	Marisa Llorens, Javier Oliver 0001	Introducing Structural Dynamic Changes in Petri Nets: Marked-Controlled Reconfigurable Nets.	ATVA	2004	DBLP DOI BibTeX RDF
35	Juanjo Noguera, Rosa M. Badia	HW/SW codesign techniques for dynamically reconfigurable architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
35	Bharat P. Dave	CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems.	DATE	1999	DBLP DOI BibTeX RDF
34	Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung	Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	2D filter design, FPGA, Singular Value Decomposition, reconfigurable logic
33	José M. García 0001, A. Flores	A Novel Approach to Improve the Performance of Interconnection Networks with Hot - Spots.	EUROMICRO	1996	DBLP DOI BibTeX RDF	physically distributed memory, single shared memory address space, two-dimensional k-ary n-cube networks, deterministic routing algorithm, interconnection networks, congestion control, message passing, multiprocessor interconnection networks, parallel machines, shared memory multiprocessors, wormhole routing, virtual channels, adaptive algorithms, performance improvement, hot-spots, reconfigurable networks, reconfigurable network
33	Imran Ahmed, Cheran M. Vithanage	Dynamic reconfiguration approach for high speed turbo decoding using circular rings.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	channel decoding, contention free, custom reconfigurable, parallel turbo, qpp, map, domain specific, vlsi
33	Chenxin Zhang, Thomas Lenart, Henrik Svensson, Viktor Öwall	Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications.	ReConFig	2009	DBLP DOI BibTeX RDF	Dynamically reconfigurable cell array, Hybrid interconnect, FFT, Coarse-grained reconfigurable architecture
32	Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner 0001, Jürgen Becker 0001	FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.	ARC	2009	DBLP DOI BibTeX RDF	design assurance, bitstream debugging, security, FPGA, Reconfigurable Computing, design verification, EDA tools
32	Adriano Idalgo, Nahri Moreano	DNA Physical Mapping on a Reconfigurable Platform.	ARC	2008	DBLP DOI BibTeX RDF	Consecutive ones problem, Software/hardware partitioning, Reconfigurable architectures
32	Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems.	ARC	2006	DBLP DOI BibTeX RDF	RSA, Elliptic Curve Cryptography (ECC), Public-Key Cryptography (PKC), Reconfigurable architecture, FPGA implementation
31	Mehrdad Majzoobi, Farinaz Koushanfar, Miodrag Potkonjak	Techniques for Design and Implementation of Secure Reconfigurable PUFs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	process variation, Reconfigurable systems, hardware security, physically unclonable functions
31	John Sachs Beeckler, Warren J. Gross	Particle graphics on reconfigurable hardware.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	FPGAs, Reconfigurable computing, particle systems, special-purpose architectures
31	Patrick Schaumont, Alex K. Jones, Steve Trimberger	Guest Editors' Introduction to Security in Reconfigurable Systems Design.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	Trojan, Trustworthy design, side-channel resistant design, physically unclonable function
31	Laïd Kahloul, Allaoua Chaoui	Code mobility modeling: a temporal labeled reconfigurable nets.	MOBILWARE	2008	DBLP DOI BibTeX RDF	formal tools, labeled reconfigurable nets, temporal labeled reconfigurable nets, code mobility, design paradigms
31	Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis	Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture.	J. Supercomput.	2007	DBLP DOI BibTeX RDF	Coarse-grained reconfigurable arrays, Data bandwidth bottleneck, Reconfigurable computing, Data reuse, Compiler techniques
31	Sakir Sezer, Ciaran Toal, Emi Garcia, Victoria Stewart	A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling.	IPDPS	2004	DBLP DOI BibTeX RDF	reconfigurable packet scheduling, SCFQ, Reconfigurable architectures, WFQ, network processing
31	Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan	Reconfigurable platforms for ubiquitous computing.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	ubiquitous computing, communication, networks-on-chip, reconfiguration, reconfigurable hardware, dynamic power management, reconfigurable processors