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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5390 occurrences of 2060 keywords
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Found 21101 publication records. Showing 21101 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
77 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 335-342, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
extensible embedded processor, reconfigurable computing, kernel, accelerator, replacement, run-time adaptation |
66 | Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen |
Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 41(1), pp. 35-47, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
heterogeneous reconfigurable multimedia systems, energy efficiency, reconfigurable computing, discrete wavelet transform, lifting scheme |
63 | Fengbin Qi, Xianyi Zhang, Shanshan Wang, Xingquan Mao |
RCC: A New Programming Language for Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009, 25-27 June 2009, Seoul, Korea, pp. 688-693, 2009, IEEE, 978-0-7695-3738-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
63 | Ronald Scrofano, Viktor K. Prasanna |
A Performance model for accelerating scientific applications on reconfigurable computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 234, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
61 | Mahmood Fazlali, Mohammad K. Fallah, Mahdy Zolghadr, Ali Zakerolhosseini |
A New Datapath Merging Method for Reconfigurable System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 157-168, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Datapath Merging, Maximum Weighted Clique Algorithm, High Level Synthesis, Reconfigurable Computing |
54 | Mounir Hamdi, J. Tong, C. W. Kin |
Fast sorting algorithms on reconfigurable array of processors with optical buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 183-188, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable array of processors, optical buses, parallel algorithms, parallel architectures, sorting, reconfigurable architectures, optical interconnections, system buses, sorting algorithms, reconfigurable array, reconfigurable arrays, parallel sorting algorithm |
54 | Katherine Compton, Scott Hauck |
Reconfigurable computing: a survey of systems and software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 34(2), pp. 171-210, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
field-programmable, manual design, FPGA, reconfigurable computing, reconfigurable architectures, reconfigurable systems, Automatic design |
54 | Francisco Barat, Rudy Lauwereins |
Reconfigurable Instruction Set Processors: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), Paris, France, June 21-23, 2000, pp. 168-173, 2000, IEEE Computer Society, 0-7695-0668-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
dynamically reconfigurable instruction set processor, reconfigurable functional unit, application specific instructions, reconfigurable computing |
54 | Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi |
CODA-R: a reconfigurable testbed for real-time parallel computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 4th International Workshop on Real-Time Computing Systems and Applications (RTCSA '97), 27-29 October 1997, Taipei, Taiwan, pp. 252-259, 1997, IEEE Computer Society, 0-8186-8073-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
CODA-R, reconfigurable testbed, real-time parallel computation, reconfigurable field programmable gate arrays, total execution time, prototype reconfigurable real-time parallel system, real-time parallel architecture, field programmable gate arrays, real-time system, processing elements, computing engine |
54 | Francisco Barat, Rudy Lauwereins, Geert Deconinck |
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 28(9), pp. 847-862, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Reconfigurable instruction set processor overview, compiler, microprocessor, reconfigurable logic |
54 | Ronald Scrofano, Maya B. Gokhale, Frans Trouw, Viktor K. Prasanna |
Accelerating Molecular Dynamics Simulations with Reconfigurable Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 19(6), pp. 764-778, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Physics, Reconfigurable hardware, Distributed architectures, Chemistry |
54 | Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich |
Task scheduling for heterogeneous reconfigurable computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 22-27, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hardware preemption, scheduling, FPGA, placement, reconfigurable computing, partial reconfiguration |
50 | Pao-Ann Hsiung, Chao-Sheng Lin, Chih-Feng Liao |
Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(3), pp. 17:1-17:30, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
scheduling, performance evaluation, partitioning, placement, design-space exploration, Reconfigurable systems |
49 | Kang Sun, Jun Zheng, Yuanyuan Li, Xuezeng Pan |
Design of a Simulator for Mesh-Based Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NPC ![In: Network and Parallel Computing, IFIP International Conference, NPC 2007, Dalian, China, September 18-21, 2007, Proceedings, pp. 526-535, 2007, Springer, 978-3-540-74783-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
simulator, reconfigurable computing, dynamic reconfiguration, reconfigurable mesh |
49 | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis |
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 38(1), pp. 17-34, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
heterogeneous reconfigurable architectures, coarse-grain reconfigurable hardware, scheduling, FPGA, partitioning, performance improvements |
49 | Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein |
Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(2), pp. 251-281, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Term Rewriting Systems (TRS), algebraic manipulation, dynamically reconfigurable systems, Fast Fourier Transform (FFT), reconfigurable computing, systolic arrays, rewriting-logic |
49 | Ali Akoglu, Aravind Dasu, Arvind Sudarsanam, Mayur Srinivasan, Sethuraman Panchanathan |
Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable media processor, recurring pattern analyzer, mobile multimedia processing, partition, dynamic reconfiguration, reconfigurable architectures, data flow graph, control flow graph, MPEG4, hardware software co-design, hardware software partitioning, routing architecture |
49 | Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, Eliseu M. Chaves Filho |
MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(5), pp. 465-481, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reconfigurable cell array, bit-correlation, dynamic reconfiguration, Single Instruction Multiple Data, multimedia applications, video compression, MPEG-2, Reconfigurable systems, data encryption, target recognition |
49 | Jinguo Liu, Yuechao Wang, Bin Li 0001, Shugen Ma, Dalong Tan |
Center-configuration selection technique for the reconfigurable modular robot. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 50(5), pp. 697-710, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
center-configuration, configuration network, reconfiguration cost matrix, center-configuration coefficient, modular robot, reconfigurable robot |
49 | Giovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto |
A Data Oriented Approach to the Design of Reconfigurable Stream Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2005, September 22-23, 2005, New York Metropolitan Area, USA, pp. 107-112, 2005, IEEE Computer Society, 0-7803-9347-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter |
A reconfigurable unit for a clustered programmable-reconfigurable processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 200-209, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, technology scaling, reconfigurable processor |
45 | Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis |
The Molen compiler for reconfigurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 6(1), pp. 6, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, reconfigurable computing, Instruction scheduling |
45 | I-Hsuan Huang, Chih-Chun Wang, Shih-Min Chu, Cheng-Zen Yang |
Function-Level Multitasking Interface Design in an Embedded Operating System with Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2007, Taipei, Taiwan, December 17-20, 2007, Proceedings, pp. 45-54, 2007, Springer, 978-3-540-77091-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
hardware function, FPGA-based computer, ?C/OS, Reconfigurable computing, multitasking |
45 | Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011 |
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(11), pp. 1436-1448, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Data communications devices, application studies resulting in better multiple-processor systems, reconfigurable hardware, wireless systems, special-purpose and application-based systems, adaptable architectures, heterogeneous (hybrid) systems, design studies, signal processing systems |
45 | Nicolas Ventroux, Stéphane Chevobbe, Frédéric Blanc 0001, Thierry Collette |
An Auto-adaptative Reconfigurable Architecture for the Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings, pp. 72-87, 2004, Springer, 3-540-23003-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
adaptative reconfigurable architecture, control parallelism, dynamic reconfiguration |
45 | Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck |
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 338-344, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
coarse grained logic, code generation, software pipelining, vliw, reconfigurable processor, spatial computation |
45 | Alan A. Bertossi, Alessandro Mei |
A Residue Number System on Reconfigurable Mesh with Applications to Prefix Sums and Approximate String Matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(11), pp. 1186-1199, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
string matching with $k$ mismatches, VLSI, residue number system, reconfigurable mesh, prefix sums, Number representation |
44 | Jochen Strunk, Toni Volkmer, Klaus Stephan, Wolfgang Rehm, Heiko Schick |
Impact of run-time reconfiguration on design and speed - A case study based on a grid of run-time reconfigurable modules inside a FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
44 | Li-Hsun Chen, Oscal T.-C. Chen, Ruey-Ling Ma |
A high-efficiency reconfigurable digital signal processor for multimedia computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 768-771, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow |
A Desktop Computer with a Reconfigurable Pentium®. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 5:1-5:15, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Pentium®, simulator, model, FPGA, architecture, operating system, reconfigurable, emulator, exploration, accelerator, processor |
40 | Saad AlKasabi, Salim Hariri |
Performance analysis of a high-speed dynamically reconfigurable LAN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 20th Conference on Local Computer Networks (LCN'95), Minneapolis, Minnesota, USA, October 16-19, 1995, pp. 236-245, 1995, IEEE Computer Society, 0-8186-7162-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
dynamically reconfigurable LAN, reconfigurable switch, highspeed multi-link ring local area network, switch reconfigurability, multi-link ring network, M/M/n, M/D/n, virtual channel occupancy probabilities, infinite state Markov model, finite state Markov model, OPNET tool, packet transfer time, virtual channel flow, performance evaluation, field programmable gate arrays, performance analysis, local area networks, reconfigurable architectures, wormhole routing, network performance, queuing systems, interconnection topologies, system throughput |
40 | Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis |
Compiler assisted architectural exploration for coarse grained reconfigurable arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 164-167, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
coarse-grained reconfigurable arrays, reconfigurable computing, modulo scheduling, architectural exploration |
40 | David R. Martinez, Tyler J. Moeller, Ken Teitelbaum |
Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(1-2), pp. 63-83, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
VLSI rader signal processor, front end high performance filtering, digital filtering mapped to reconfigurable computing, commercial FPGA hardware, reconfigurable hardware |
40 | Akihiro Matsuura, Akira Nagoya |
Summation Algorithms on Constrained Reconfigurable Meshes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '99), 23-25 June 1999, Fremantle, Australia, pp. 400-405, 1999, IEEE Computer Society, 0-7695-0231-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
constrained reconfigurable mesh, Bit summation, parallel algorithm, reconfigurable mesh |
40 | Koji Nakano, Stephan Olariu |
An Efficient Algorithm for Row Minima Computations on Basic Reconfigurable Meshes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 9(6), pp. 561-569, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Monotone matrices, totally monotone matrices, row minima, basic reconfigurable meshes, cellular system design, VLSI design, search problems, reconfigurable meshes, facility location problems |
40 | Lizyamma Kurian, Daniel Brewer, Eugene John |
Design of a highly reconfigurable interconnect for array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 321-325, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
reconfigurable interconnect, static-RAM programming technology, faulty elements, fault-tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, network topology, reconfigurable architectures, array processors, interconnection topologies, mesh topologies |
40 | Kuen-Cheng Chiang, Zhi-Wei Chen, Jean Jyh-Jiun Shann |
Design and implementation of a reconfigurable hardware for secure embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsiaCCS ![In: Proceedings of the 2006 ACM Symposium on Information, Computer and Communications Security, ASIACCS 2006, Taipei, Taiwan, March 21-24, 2006, pp. 364, 2006, ACM, 1-59593-272-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
secured embedded system, AES, RSA, reconfigurable architecture, DES, processing element |
40 | Ronald Scrofano, Viktor K. Prasanna |
Molecular dynamics - Preliminary investigation of advanced electrostatics in molecular dynamics on reconfigurable computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 90, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, reconfigurable, molecular dynamics, electrostatics |
40 | Russell Tessier, Wayne P. Burleson |
Reconfigurable Computing for Digital Signal Processing: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(1-2), pp. 7-27, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
FPGA, survey, reconfigurable computing, signal processing |
40 | Venkatavasu Bokka, Himabindu Gurla, Stephan Olariu, James L. Schwing |
Constant-Time Algorithms for Constrained Triangulations on Reconfigurable Meshes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 9(11), pp. 1057-1072, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Computer-aided manufacturing, constrained triangulations, constant time algorithms, robotics, CAD, VLSI design, reconfigurable meshes, computer-aided geometric design |
40 | Tatsuya Hayashi, Koji Nakano, Stephan Olariu |
An O((log log n)2) Time Algorithm to Compute the Convex Hull of Sorted Points on Reconfigurable Meshes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 9(12), pp. 1167-1179, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
pattern recognition, mobile computing, image processing, Convex hulls, morphology, reconfigurable meshes |
40 | Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 290-295, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Wesley Peck, Erik K. Anderson, Jason Agron, Jim Stevens, Fabrice Baijot, David Andrews 0001 |
Hthreads: A Computational Model for Reconfigurable Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Wenyin Fu, Katherine Compton |
A Simulation Platform for Reconfigurable Computing Research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-7, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Wenyin Fu, Katherine Compton |
An Execution Environment for Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 17-20 April 2005, Napa, CA, USA, Proceedings, pp. 149-158, 2005, IEEE Computer Society, 0-7695-2445-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Christian Haubelt |
Design Space Exploration for Distributed Hardware Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 1171, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger |
A Synthesis System For Bus-Based Wavefront Array Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 274-283, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations |
37 | Vikas Aggarwal, Alan D. George, Kishore Yalamanchili, Changil Yoon, Herman Lam, Greg Stitt |
Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPRCTA@SC ![In: Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications, HPRTCA 2009, November 15, 2009, Portland, Oregon, USA, pp. 47-54, 2009, ACM, 978-1-60558-721-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
parallel programming, programming language, reconfigurable computing, productivity, portability, programming model |
37 | Katarzyna Leijten-Nowak, Jef L. van Meerbergen |
Embedded Reconfigurable Logic Core for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 89-101, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon |
Stream Computations Organized for Reconfigurable Execution (SCORE). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 605-614, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | David Robinson, Patrick Lysaght |
Verification of Dynamically Reconfigurable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 141-150, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Esam El-Araby, Iván González 0004, Tarek A. El-Ghazawi |
Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(4), pp. 21:1-21:23, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
field programmable gate arrays (FPGA), High performance computing, reconfigurable computing, dynamic partial reconfiguration |
35 | Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab |
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 86-91, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reconfigurable instant-on system, ultralow-power reconfigurable computing, complementary nanoelectromechanical carbon nanotube switches, coplanar carbon nanotubes, low operation voltages, built-in energy storage, CNEMS, stable on-off state, latching mechanism, nonvolatile memory-mode operation, CMOS transistors, system development, leakage current |
35 | Grigoris Dimitroulakos, Michalis D. Galanis, Nikos Kostaras, Costas E. Goutis |
A unified evaluation framework for coarse grained reconfigurable array architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007, pp. 161-172, 2007, ACM, 978-1-59593-683-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
coarse-grained reconfigurable arrays, reconfigurable romputing, Modulo scheduling, architectural exploration |
35 | Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo |
The design of dynamically reconfigurable datapath coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(2), pp. 361-384, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
coarse-grain reconfigurable fabric, reconfigurable datapath, Loop pipelining, interconnection design, datapath synthesis |
35 | Hossam A. ElGindy, Lachlan Wetherall |
A simple Voronoi diagram algorithm for a reconfigurable mesh. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 296-303, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Voronoi diagram algorithm, planar points, worst case running, communication diameter, scheduling, load balancing, computational geometry, reconfigurable architectures, reconfigurable mesh |
35 | Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, Thomas Wild |
Reconfigurable Processing Units vs. Reconfigurable Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Architectures ![In: Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
35 | Minghui Wang, Shugen Ma, Bin Li 0001, Yuechao Wang |
Configuration representation and reconfiguration optimization for the reconfigurable robots with independent manipulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 52(4), pp. 674-687, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
reconfigurable robots with independent manipulation, configuration representation, reconfiguration optimization |
35 | Like Yan, Gang Wang, Tianzhou Chen |
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 281, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic adaption, reconfigurable system, loop unrolling, loop accelerator |
35 | Jinguo Liu, Shugen Ma, Yuechao Wang, Bin Li 0001 |
Network-based reconfiguration routes for a self-reconfigurable robot. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(10), pp. 1532-1546, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
reconfiguration route, network-based reconfiguration, configuration network, modular robot, self-reconfigurable robot |
35 | Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi |
Compiling custom instructions onto expression-grained reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 51-60, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
horizontal microprogramming, compilers, instruction set extensions, coarse-grained reconfigurable architectures, data-flow architectures |
35 | Valeri Kirischian, Vadim Geurkov, Lev Kirischian |
A multi-mode video-stream processor with cyclically reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008, pp. 105-106, 2008, ACM, 978-1-60558-077-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cost-performance ratio, video-stream processor, FPGA, computer architecture, reconfigurable computing, dynamic reconfiguration, pre-fetching, temporal partitioning |
35 | Ling Zhuo, Viktor K. Prasanna |
Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Reconfigurable Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 18(4), pp. 433-448, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
computations on matrices, field-programmable gate arrays, parallel algorithms, Scientific computing, reconfigurable hardware |
35 | Mary Mehrnoosh Eshaghian-Wilner, Alexander Khitun, Shiva Navab, Kang L. Wang |
The spin-wave nanoscale reconfigurable mesh and the labeling problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 3(2), pp. 5, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
nanoscale architectures, image processing, reconfigurable mesh, Spin waves |
35 | Esben Hallundbæk Østergaard, Kristian Kassow, Richard A. Beck, Henrik Hautop Lund |
Design of the ATRON lattice-based self-reconfigurable robot. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Auton. Robots ![In: Auton. Robots 21(2), pp. 165-183, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Design, Robotics, Morphology, Mechanics, Self-reconfigurable |
35 | Wei Xu, Shigang Wang, An-Lin Wang, Guobao Wang |
Towards an Efficient Self-organizing Reconfiguration Method for Self-reconfigurable Robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 37(4), pp. 415-425, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
descriptive model, metamorphic rules, self-organizing, modular robots, self-reconfigurable robots |
35 | Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka |
Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 28-31, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SRAM test, SRAM-based reconfigurable cell, memory tester, marching test |
35 | Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh, Tobias G. Noll |
Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(2), pp. 117-126, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
heterogeneous reconfigurable systems, dedicated ASICs, coprocessor board, CardBus, multimedia applications, text search |
35 | Venkatavasu Bokka, Koji Nakano, Stephan Olariu, James L. Schwing, Larry Wilson |
Optimal Algorithms for the Multiple Query Problem on Reconfigurable Meshes, with Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(9), pp. 875-887, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
pattern recognition, parallel algorithms, image processing, robotics, Query processing, computational geometry, database design, morphology, reconfigurable mesh |
35 | Alan A. Bertossi, Alessandro Mei |
Constant Time Dynamic Programming on Directed Reconfigurable Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(6), pp. 529-536, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
directed links, VLSI, dynamic programming, shortest paths, Reconfigurable architectures, longest common subsequence |
35 | Ronald D. Williams, Brian D. Kuebert |
Reconfigurable Pipelines in VLIW Execution Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 298-299, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
very long instruction word, pipelines, reconfigurable computing |
35 | Stephan Olariu, James L. Schwing, Jingyuan Zhang |
Efficient Image Computations on Reconfigurable Meshes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 92 - VAPP V, Second Joint International Conference on Vector and Parallel Processing, Lyon, France, September 1-4, 1992, Proceedings, pp. 589-594, 1992, Springer, 3-540-55895-0. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
bus systems, computer vision, image processing, segmentation, robotics, convex hull, reconfigurable meshes, area, perimeter, component labeling |
35 | Daniele Piazza, John Kountouriotis, Michele d'Amico, Kapil R. Dandekar |
A technique for antenna configuration selection for reconfigurable circular patch arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 8(3), pp. 1456-1467, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Alfred Grau, Hamid Jafarkhani, Franco De Flaviis |
A reconfigurable multiple-input multiple-output communication system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 7(5-1), pp. 1719-1733, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Guy Gogniat, Tilman Wolf, Wayne P. Burleson, Jean-Philippe Diguet, Lilian Bossuet, Romain Vaslin |
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(2), pp. 144-155, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro |
Balancing reconfigurable data path resources according to application requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Kehuai Wu, Jan Madsen |
COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007, pp. 128-136, 2007, IEEE, 1-4244-1058-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis |
Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 352-362, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis |
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Ronald Scrofano, Maya B. Gokhale, Frans Trouw, Viktor K. Prasanna |
Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 23-34, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Yeong-Kang Lai, Lien-Fei Chen, Jian-Chou Chen, Chun-Wei Chiu |
A two-way SIMD-based reconfigurable computing architecture for multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4578-4581, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Jonathan E. Luntz, James R. Moyne, Dawn M. Tilbury |
On-line control reconfiguration at the machine and cell levels: case studies from the reconfigurable factory testbed. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETFA ![In: Proceedings of 10th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2005, September 19-22, 2005, Catania, Italy, 2005, IEEE, 0-7803-9401-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Jens Braunes, Steffen Köhler, Rainer G. Spallek |
RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Organic and Pervasive Computing - ARCS 2004, International Conference on Architecture of Computing Systems, Augsburg, Germany, March 23-26, 2004, Proceedings, pp. 156-166, 2004, Springer, 3-540-21238-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Marisa Llorens, Javier Oliver 0001 |
Introducing Structural Dynamic Changes in Petri Nets: Marked-Controlled Reconfigurable Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis: Second International Conference, ATVA 2004, Taipei, Taiwan, ROC, October 31-November 3, 2004. Proceedings, pp. 310-323, 2004, Springer, 3-540-23610-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Juanjo Noguera, Rosa M. Badia |
HW/SW codesign techniques for dynamically reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(4), pp. 399-415, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Bharat P. Dave |
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 97-104, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung |
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(4), pp. 24:1-24:28, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
2D filter design, FPGA, Singular Value Decomposition, reconfigurable logic |
33 | José M. García 0001, A. Flores |
A Novel Approach to Improve the Performance of Interconnection Networks with Hot - Spots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 215-222, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
physically distributed memory, single shared memory address space, two-dimensional k-ary n-cube networks, deterministic routing algorithm, interconnection networks, congestion control, message passing, multiprocessor interconnection networks, parallel machines, shared memory multiprocessors, wormhole routing, virtual channels, adaptive algorithms, performance improvement, hot-spots, reconfigurable networks, reconfigurable network |
33 | Imran Ahmed, Cheran M. Vithanage |
Dynamic reconfiguration approach for high speed turbo decoding using circular rings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 475-480, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
channel decoding, contention free, custom reconfigurable, parallel turbo, qpp, map, domain specific, vlsi |
33 | Chenxin Zhang, Thomas Lenart, Henrik Svensson, Viktor Öwall |
Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 338-343, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Dynamically reconfigurable cell array, Hybrid interconnect, FFT, Coarse-grained reconfigurable architecture |
32 | Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner 0001, Jürgen Becker 0001 |
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 62-73, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
design assurance, bitstream debugging, security, FPGA, Reconfigurable Computing, design verification, EDA tools |
32 | Adriano Idalgo, Nahri Moreano |
DNA Physical Mapping on a Reconfigurable Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, pp. 27-38, 2008, Springer, 978-3-540-78609-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Consecutive ones problem, Software/hardware partitioning, Reconfigurable architectures |
32 | Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede |
Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 347-357, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RSA, Elliptic Curve Cryptography (ECC), Public-Key Cryptography (PKC), Reconfigurable architecture, FPGA implementation |
31 | Mehrdad Majzoobi, Farinaz Koushanfar, Miodrag Potkonjak |
Techniques for Design and Implementation of Secure Reconfigurable PUFs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(1), pp. 5:1-5:33, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
process variation, Reconfigurable systems, hardware security, physically unclonable functions |
31 | John Sachs Beeckler, Warren J. Gross |
Particle graphics on reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(3), pp. 15:1-15:27, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGAs, Reconfigurable computing, particle systems, special-purpose architectures |
31 | Patrick Schaumont, Alex K. Jones, Steve Trimberger |
Guest Editors' Introduction to Security in Reconfigurable Systems Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(1), pp. 1:1-1:6, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Trojan, Trustworthy design, side-channel resistant design, physically unclonable function |
31 | Laïd Kahloul, Allaoua Chaoui |
Code mobility modeling: a temporal labeled reconfigurable nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOBILWARE ![In: Proceedings of the 1st International Conference on MOBILe Wireless MiddleWARE, Operating Systems, and Applications, MOBILWARE 2008, Innsbruck, Austria, February 13 - 15, 2008, pp. 34, 2008, 978-1-59593-984-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
formal tools, labeled reconfigurable nets, temporal labeled reconfigurable nets, code mobility, design paradigms |
31 | Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis |
Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 40(2), pp. 127-157, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Coarse-grained reconfigurable arrays, Data bandwidth bottleneck, Reconfigurable computing, Data reuse, Compiler techniques |
31 | Sakir Sezer, Ciaran Toal, Emi Garcia, Victoria Stewart |
A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
reconfigurable packet scheduling, SCFQ, Reconfigurable architectures, WFQ, network processing |
31 | Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan |
Reconfigurable platforms for ubiquitous computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 377-389, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ubiquitous computing, communication, networks-on-chip, reconfiguration, reconfigurable hardware, dynamic power management, reconfigurable processors |
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