Search results for "runahead"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
254	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Techniques for Efficient Processing in Runahead Execution Engines.	ISCA	2005	DBLP DOI BibTeX RDF
235	Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout	MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
147	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Kilo-instruction processors, runahead and prefetching.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	runahead, prefetching, speculative execution, memory wall, Kilo-instruction processors
122	Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt	Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors.	HPCA	2003	DBLP DOI BibTeX RDF
103	Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt	On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor.	IEEE Comput. Archit. Lett.	2005	DBLP DOI BibTeX RDF
101	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	value prediction, memory-level parallelism, runahead execution, Single data stream architectures
90	Polychronis Xekalakis, Nikolas Ioannou, Marcelo Cintra	Combining thread level speculation helper threads and runahead execution.	ICS	2009	DBLP DOI BibTeX RDF	multi-cores, thread-level speculation, helper threads, runahead execution
90	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance.	IEEE Micro	2006	DBLP DOI BibTeX RDF	memory latency tolerance, processors, Runahead execution
90	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	processor performance modeling, speculative execution, runahead execution, Single data stream architectures
84	Martin Karlsson, Erik Hagersten	Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution.	IPDPS	2007	DBLP DOI BibTeX RDF
84	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns.	MICRO	2005	DBLP DOI BibTeX RDF
57	Yuan Chou, Brian Fahs, Santosh G. Abraham	Microarchitecture Optimizations for Exploiting Memory-Level Parallelism.	ISCA	2004	DBLP DOI BibTeX RDF
55	Milad Hashemi, Yale N. Patt	Filtered runahead execution with a runahead buffer.	MICRO	2015	DBLP DOI BibTeX RDF
46	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Runahead Threads to improve SMT performance.	HPCA	2008	DBLP DOI BibTeX RDF
46	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Runahead Threads: Reducing Resource Contention in SMT Processors.	PACT	2007	DBLP DOI BibTeX RDF
46	Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt	Runahead Execution: An Effective Alternative to Large Instruction Windows.	IEEE Micro	2003	DBLP DOI BibTeX RDF
44	Peng Zhou, Soner Önder	Improving single-thread performance with fine-grain state maintenance.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	processor state, runahead, simultaneous multi-threading, checkpoint, recovery
44	Ilya Ganusov, Martin Burtscher	On the importance of optimizing the configuration of stream prefetchers.	Memory System Performance	2005	DBLP DOI BibTeX RDF	hardware prefetching, stream prefetcher, runahead execution
38	Luis Ceze, Karin Strauss, James Tuck 0001, Josep Torrellas, Jose Renau	CAVA: Using checkpoint-assisted value prediction to hide L2 misses.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	checkpointed processor architectures, multiprocessor, memory hierarchies, Value prediction
27	Chaoqun Shen, Gang Qu 0001, Jiliang Zhang 0002	SPECRUN: The Danger of Speculative Runahead Execution in Processors.	CoRR	2023	DBLP DOI BibTeX RDF
27	Ajeya Naithani, Jaime Roelandts, Sam Ainsworth 0001, Timothy M. Jones 0001, Lieven Eeckhout	Decoupled Vector Runahead.	MICRO	2023	DBLP DOI BibTeX RDF
27	Mohammad Bakhshalipour, Mohamad Qadri, Dominic Guri, Seyed Borna Ehsani, Maxim Likhachev, Phillip B. Gibbons	Runahead A: Speculative Parallelism for A with Slow Expansions.	ICAPS	2023	DBLP DOI BibTeX RDF
27	Ajeya Naithani, Sam Ainsworth 0001, Timothy M. Jones 0001, Lieven Eeckhout	Vector Runahead for Indirect Memory Accesses.	IEEE Micro	2022	DBLP DOI BibTeX RDF
27	Ajeya Naithani, Lieven Eeckhout	Reliability-Aware Runahead.	HPCA	2022	DBLP DOI BibTeX RDF
27	Stephen Pruett, Yale N. Patt	Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches.	MICRO	2021	DBLP DOI BibTeX RDF
27	Hikaru Takayashiki, Masayuki Sato 0001, Kazuhiko Komatsu, Hiroaki Kobayashi	Register Flush-free Runahead Execution for Modern Vector Processors.	SBAC-PAD	2021	DBLP DOI BibTeX RDF
27	Ajeya Naithani, Sam Ainsworth 0001, Timothy M. Jones 0001, Lieven Eeckhout	Vector Runahead.	ISCA	2021	DBLP DOI BibTeX RDF
27	Fatemeh Golshan, Mohammad Bakhshalipour, Mehran Shakerinava, Ali Ansari 0001, Pejman Lotfi-Kamran, Hamid Sarbazi-Azad	Harnessing Pairwise-Correlating Data Prefetching With Runahead Metadata.	IEEE Comput. Archit. Lett.	2020	DBLP DOI BibTeX RDF
27	Susumu Mashimo, Ryota Shioya, Koji Inoue	Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core.	HPC Asia	2020	DBLP DOI BibTeX RDF
27	Ajeya Naithani, Josué Feliu, Almutaz Adileh, Lieven Eeckhout	Precise Runahead Execution.	HPCA	2020	DBLP DOI BibTeX RDF
27	Danilo Gallo, Shreepriya Shreepriya, Jutta Willamowski	RunAhead: Exploring Head Scanning based Navigation for Runners.	CHI	2020	DBLP DOI BibTeX RDF
27	Danilo Gallo, Shreepriya Shreepriya, Jutta Willamowski	RunAhead: Providing Head Scanning based Navigation feedback.	CHI Extended Abstracts	2020	DBLP DOI BibTeX RDF
27	Ajeya Naithani, Josué Feliu, Almutaz Adileh, Lieven Eeckhout	Precise Runahead Execution.	IEEE Comput. Archit. Lett.	2019	DBLP DOI BibTeX RDF
27	Shane T. Fleming, David B. Thomas	Using Runahead Execution to Hide Memory Latency in High Level Synthesis.	FCCM	2017	DBLP DOI BibTeX RDF
27	Milad Hashemi, Onur Mutlu, Yale N. Patt	Continuous runahead: Transparent hardware acceleration for memory intensive workloads.	MICRO	2016	DBLP DOI BibTeX RDF
27	Zimo Li, Joshua San Miguel, Natalie D. Enright Jerger	The runahead network-on-chip.	HPCA	2016	DBLP DOI BibTeX RDF
27	Xi Tao, Qi Zeng 0006, Jih-Kwon Peir, Shih-Lien Lu	Runahead Cache Misses Using Bloom Filter.	PDCAT	2016	DBLP DOI BibTeX RDF
27	Sonya R. Wolff, Ronald D. Barnes	Revisiting Using the Results of Pre-Executed Instructions in Runahead Processors.	IEEE Comput. Archit. Lett.	2014	DBLP DOI BibTeX RDF
27	Kaveh Aasaraai, Andreas Moshovos	NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution.	Int. J. Reconfigurable Comput.	2012	DBLP DOI BibTeX RDF
27	Kaveh Aasaraai, Andreas Moshovos	SPREX: A soft processor with Runahead execution.	ReConFig	2012	DBLP DOI BibTeX RDF
27	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Onur Mutlu, Mateo Valero	Efficient runahead threads.	PACT	2010	DBLP DOI BibTeX RDF
27	Harold W. Cain, Priya Nagpurkar	Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor.	ISPASS	2010	DBLP DOI BibTeX RDF
27	Tanausú Ramírez	Runahead threads.		2010	RDF
27	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Code Semantic-Aware Runahead Threads.	ICPP	2009	DBLP DOI BibTeX RDF
25	Walter Yuan-Hwa Li, Chin-Ling Huang, Chung-Ping Chung	Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity.	ICPP	2011	DBLP DOI BibTeX RDF	Execute Ahead, Hardware Speculation, Instruction-Level Parallelism, Processor Architecture, Memory-Level Parallelism, Runahead Execution
25	Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu	Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	cache-miss tolerance, prefetching, out-of-order execution, Runahead execution
25	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	cache filtering, speculative memory references, Caches, runahead execution, cache pollution
19	Weifeng Zhang 0003, Dean M. Tullsen, Brad Calder	Accelerating and Adapting Precomputation Threads for Effcient Prefetching.	HPCA	2007	DBLP DOI BibTeX RDF
19	Ilya Ganusov, Martin Burtscher	Future execution: A prefetching mechanism that uses multiple cores to speed up single threads.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	Future execution, chip multiprocessors, prefetching, memory wall
19	Zhen Yang, Xudong Shi 0003, Feiqi Su, Jih-Kwon Peir	Overlapping dependent loads with addressless preload.	PACT	2006	DBLP DOI BibTeX RDF	instruction and issue window, pointer-chasing loads, data prefetching, memory-level parallelism
19	Ilya Ganusov, Martin Burtscher	Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors.	IEEE PACT	2005	DBLP DOI BibTeX RDF
19	Matthew Curtis-Maury, Tanping Wang	Integrating Multiple Forms of Multithreaded Execution on multi-SMT Systems: A Study with Scientific Applications.	QEST	2005	DBLP DOI BibTeX RDF
19	Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu	"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense.	MICRO	2005	DBLP DOI BibTeX RDF
19	Sorin Iacobovici, Lawrence Spracklen, Sudarshan Kadambi, Yuan Chou, Santosh G. Abraham	Effective stream-based and execution-based data prefetching.	ICS	2004	DBLP DOI BibTeX RDF	hardware prefetcher, multiple strides, stream prefetching