Search results for "sense-amp"

Found 9 publication records. Showing 9 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
57	Michael A. Turi, José G. Delgado-Frias	High-performance low-power AND and Sense-Amp address decoders with selective precharging.	ISCAS	2008	DBLP DOI BibTeX RDF
38	Daniel J. Deleganes, Micah Barany, George L. Geannopoulos, Kurt Kreitzer, Anant P. Singh, Sapumal B. Wijeratne	Low voltage swing logic circuits for a Pentium 4 processor integer core.	DAC	2004	DBLP DOI BibTeX RDF	LVS, Pentium® 4 processor, integer core, low voltage swing, sense-amp, microprocessor, rotator, adder
31	Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka	Statistical yield analysis of silicon-on-insulator embedded DRAM.	ISQED	2009	DBLP DOI BibTeX RDF
26	Robert M. Houle	Simple Statistical Analysis Techniques to Determine Optimum Sense Amp Set Times.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
26	Robert M. Houle	Simple Statistical Analysis Techniques to Determine Minimum Sense Amp Set Times.	CICC	2007	DBLP DOI BibTeX RDF
26	Ciaran J. Brennan, Steven Eustis, John Goss, A. Humphrey, Michael Ouellette, Jeremy Rowland, Michael Fragano	BIST controlled variable sense amp timing for 90nm embedded SRAM.	CICC	2004	DBLP DOI BibTeX RDF
22	Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella	Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns.	HiPC	2006	DBLP DOI BibTeX RDF
15	Soner Yaldiz, Umut Arslan, Xin Li 0001, Larry T. Pileggi	Efficient statistical analysis of read timing failures in SRAM circuits.	ISQED	2009	DBLP DOI BibTeX RDF
15	John Poulton	An Embedded DRAM for CMOS ASICs.	ARVLSI	1997	DBLP DOI BibTeX RDF

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