Search results for "sign-off"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
41	Sari Onaissi, Khaled R. Heloue, Farid N. Najm	Clock skew optimization via wiresizing for timing sign-off covering all process corners.	DAC	2009	DBLP DOI BibTeX RDF	clock skew optimization, parameterized timing analysis, sign-off, wiresizing, variability
34	Alan Su 0002, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee	Eliminating False Loops Caused by Sharing in Control Path.	ISSS	1996	DBLP DOI BibTeX RDF	false loops, control path sharing, timing validation, design sign-off phase, data path sharing, control logic sharing, removal algorithm, computation complexity, high level synthesis, high level synthesis, filter, resource sharing, logic minimization
25	Harry Foster	Applied Boolean Equivalence Verification and RTL Static Sign-Off.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
25	Mohammad Ghasemisharif, Amrutha Ramesh, Stephen Checkoway, Chris Kanich, Jason Polakis	O Single Sign-Off, Where Art Thou? An Empirical Analysis of Single Sign-On Account Hijacking and Session Management on the Web.	USENIX Security Symposium	2018	DBLP BibTeX RDF
24	Mark Redford, Joseph Sawicki, Prasad Subramaniam, Cliff Hou, Yervant Zorian, Kimon Michaels	DFM: don't care or competitive weapon?	DAC	2009	DBLP DOI BibTeX RDF	RDR, physical verification, sign-off, yield, DFM, design-for-manufacturing, design rules, manufacturing variability, DRC
24	Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith 0001, Nikil D. Dutt, Giovanni Mancini	ESL hand-off: fact or EDA fiction?	DAC	2008	DBLP DOI BibTeX RDF	sign-off, specification, formalism, ESL, hand-off
18	Emre Tuncer, Jordi Cortadella, Luciano Lavagno	Enabling adaptability through elastic clocks.	DAC	2009	DBLP DOI BibTeX RDF	low power design, GALS, desynchronization, adaptive voltage scaling
18	Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman A. Solovyev, Jacob A. Abraham	A timing methodology considering within-die clock skew variations.	SoCC	2008	DBLP DOI BibTeX RDF
18	Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap	Fast Interconnect and Gate Timing Analysis for Performance Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
18	Tim Fox, Lou Covey, Susan Mack, David Heacock, Ed P. Huijbregts, Vess Johnson, Avner Kornfeld, Andrew Yang, Paul S. Zuchowski	Should our power approach be current?	DAC	2005	DBLP DOI BibTeX RDF	low-power design, energy consumption, power analysis, leakage current, dynamic power, static power
18	Jie Yang 0010, Luigi Capodieci, Dennis Sylvester	Advanced timing analysis based on post-OPC extraction of critical dimensions.	DAC	2005	DBLP DOI BibTeX RDF	process CD, layout, OPC, design flow
16	Farimah Farahmandi, Ankur Srivastava 0001, Giorgio Di Natale, Mark M. Tehranipoor	Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle.	ACM J. Emerg. Technol. Comput. Syst.	2023	DBLP DOI BibTeX RDF
16	Surajit Bhattacherjee, Dipankar Pal	IP Transformation Initiatives to Generate Scalable Functional Verification Collaterals for Smart Reusability and Reduced Effort for Sign-off.	ICNC	2023	DBLP DOI BibTeX RDF
16	Yufei Chen, Xiao Dong, Wei-Kai Shih, Cheng Zhuo	Invited Paper: Unleashing the Potential of Machine Learning: Harnessing the Dynamics of Supply Noise for Timing Sign-Off.	ICCAD	2023	DBLP DOI BibTeX RDF
16	Nandika R, Varsha M, Samhitha Bhat M, Prabhavathi P	SUTRA : Methodology and Sign-off.	ICCCNT	2023	DBLP DOI BibTeX RDF
16	Siting Liu 0002, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu 0001, Martin D. F. Wong	Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement.	DAC	2023	DBLP DOI BibTeX RDF
16	Giuliano Sisto, Rongmei Chen, Richard Chou, Geert Van der Plas, Eric Beyne, Rod Metcalfe, Dragomir Milojevic	Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited).	SLIP	2021	DBLP DOI BibTeX RDF
16	Minji Lee, Changseok Choi, Donghyeon Seo, Byeongjun Bang, Yongseok Kang, Woohyun Paik	Improving Analysis Coverage for Dynamic IR Drop Sign-off in FinFET SoC Design.	ISOCC	2020	DBLP DOI BibTeX RDF
16	Nikhil R. Pal	Friends, It Is My Time to Sign Off! [President's Message].	IEEE Comput. Intell. Mag.	2019	DBLP DOI BibTeX RDF
16	Christian Schlünder, Katja Waschneck, Peter Rotter, Susanne Lachenmann, Hans Reisinger, Franz Ungar, Georg Georgakos	From Device Aging Physics to Automated Circuit Reliability Sign Off.	IRPS	2019	DBLP DOI BibTeX RDF
16	Pranav Ashar, Vinod Viswanath	Closing the Verification Gap with Static Sign-off.	ISQED	2019	DBLP DOI BibTeX RDF
16	Norman Chang, Ajay Baranwal, Hao Zhuang, Ming-Chih Shih, Rahul Rajan, Yaowei Jia, Hui-Lun Liao, Ying-Shiun Li, Ting Ku, Rex Lin	Machine learning based generic violation waiver system with application on electromigration sign-off.	ASP-DAC	2018	DBLP DOI BibTeX RDF
16	George Gonzalez, Murari Mani, Mahesh Sharma	Large-scale multi-corner leakage optimization under the sign-off timing environment.	ISQED	2015	DBLP DOI BibTeX RDF
16	Vaibhav Rastogi, Ankit Agrawal 0001	All your Google and Facebook logins are belong to us: A case for single sign-off.	IC3	2015	DBLP DOI BibTeX RDF
16	Ajay Kashyap, Soenke Grimpen, Shyam Sundaramoorthy	Achieving power and reliability sign-off for automotive semiconductor designs.	DAC	2015	DBLP DOI BibTeX RDF
16	Kwang Chien Yee	An evaluation of clinician's view on electronic pathology reporting sign off and patient safety.	HIC	2013	DBLP DOI BibTeX RDF
16	Hamed Abrishami, Jinan Lou, Jeff Qin, Jürgen Frößl, Massoud Pedram	Post sign-off leakage power optimization.	DAC	2011	DBLP DOI BibTeX RDF
9	Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira	Generating realistic stimuli for accurate power grid analysis.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	stimuli generation, simulation, verification, Power grid, ground bounce, voltage drop
9	Pradip A. Thaker	Holistic verification: myth or magic bullet?	DAC	2009	DBLP DOI BibTeX RDF	SoC verification, mixed-signal verification, power management verification, emulation
9	Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik	A parametric approach for handling local variation effects in timing analysis.	DAC	2009	DBLP DOI BibTeX RDF	on chip variation (OCV), timing, parametric analysis
9	Ali Dasdan, Ivan Hom	Handling inverted temperature dependence in static timing analysis.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	timing corners, voltage dependence, Static timing analysis, temperature dependence
9	Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar	Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times.	ISQED	2006	DBLP DOI BibTeX RDF
9	Mariagrazia Graziano, Cristiano Forzan, Davide Pandini	Power Supply Selective Mapping for Accurate Timing Analysis.	PATMOS	2005	DBLP DOI BibTeX RDF
9	Cristiano Forzan, Davide Pandini	Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis.	DATE	2005	DBLP DOI BibTeX RDF
9	Nobuyuki Nishiguchi	An advance RTL to GDS2 design methodology for 90 nm and below system LSIs to solve timing closure, signal integrity and design for manufacturing.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
9	Cristiano Forzan, Davide Pandini	A complete methodology for an accurate static noise analysis.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	noise propagation, crosstalk, signal integrity
9	Tobias Thiel	Have I Really Met Timing? - Validating PrimeTime Timing Reports with Spice.	DATE	2004	DBLP DOI BibTeX RDF
9	Srivaths Ravi 0001, Anand Raghunathan, Srimat T. Chakradhar	Efficient RTL Power Estimation for Large Designs.	VLSI Design	2003	DBLP DOI BibTeX RDF
9	Jindrich Zejda, Paul Frain	General framework for removal of clock network pessimism.	ICCAD	2002	DBLP DOI BibTeX RDF	clock network reconvergence, voltage and temperature delay variation, process, static timing analysis, deep sub-micron
9	Eric Dupont, Michael Nicolaidis	Robustness IPs for Reliability and Security of SoCs.	ITC	2002	DBLP DOI BibTeX RDF
9	Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi	A multilevel engine for fast power simulation of realistic inputstreams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
9	Alan Su 0002, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee	Eliminating false loops caused by sharing in control path.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	control path, false loop
9	Ralph H. J. M. Otten	Global wires: harmful?.	ISPD	1998	DBLP DOI BibTeX RDF
9	Rajesh K. Gupta 0001, Yervant Zorian	Introducing Core-Based System Design.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF