Search results for "skew-tolerant"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
72	David L. Harris, Mark Horowitz, Dean Liu	Timing analysis including clock skew.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
57	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Optimal Timing for Skew-Tolerant High-Speed Domino Logic.	ISVLSI	2002	DBLP DOI BibTeX RDF	keeper, optimal timing, noise, skew, domino logic, dynamic circuit
54	Sungwook Kim, Gerald E. Sobelman	Efficient digit-serial FIR filters with skew-tolerant domino.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
54	Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang	Skew-tolerant high-speed (STHS) domino logic.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
47	Adam Wagner, Darius Buntinas, Dhabaleswar K. Panda 0001, Ron Brightwell	Application-Bypass Reduction for Large-Scale Clusters.	CLUSTER	2003	DBLP DOI BibTeX RDF
39	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Timing constraints for domino logic gates with timing-dependent keepers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
38	Steve Hung-Lung Tu, Chih-Hung Yen	A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques.	APCCAS	2006	DBLP DOI BibTeX RDF
30	Yohan J. Roh, Jae Ho Kim, Yon Dohn Chung, Jin Hyun Son, Myoung-Ho Kim	Hierarchically organized skew-tolerant histograms for geographic data objects.	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	query optimization, spatial databases, histograms
30	Mario Blaum, Jehoshua Bruck, Levon H. Khachatrian	Constructions of skew-tolerant and skew-detecting codes.	IEEE Trans. Inf. Theory	1993	DBLP DOI BibTeX RDF
23	David L. Harris, Stuart F. Oberman, Mark Horowitz	SRT Division Architectures and Implementations.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	skew-tolerant, Computer arithmetic, floating point units, SRT division, domino circuits
20	Chul Soo Kim, Joo-Seong Kim, Bai-Sun Kong, Yongsam Moon, Young-Hyun Jun	Presetting pulse-based flip-flop.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Oleg Okun, Matti Pietikäinen	Automatic Ground-Truth Generation for Skew-Tolerance Evaluation of Document Layout Analysis Methods.	ICPR	2000	DBLP DOI BibTeX RDF
18	Tingting Zhang, Qian Xiang, Sen Zhang, Lei Liu, Tianjian Zuo	A High-skew-tolerant and Hardware-efficient Adaptive Equalizer for Short-reach Coherent Transmission.	OFC	2021	DBLP BibTeX RDF
18	Tao Gao, Yanfei Guo, Boyu Zhang 0002, Pietro Cicotti, Yutong Lu, Pavan Balaji, Michela Taufer	Memory-Efficient and Skew-Tolerant MapReduce Over MPI for Supercomputing Systems.	IEEE Trans. Parallel Distributed Syst.	2020	DBLP DOI BibTeX RDF
18	Hyung-Joon Chi, Chang-Kyo Lee, Junghwan Park, Jin-Seok Heo, Jaehoon Jung, Dongkeon Lee, Dae-Hyun Kim 0003, Dukha Park, Kihan Kim, Sang-Yun Kim 0001, Jinsol Park, Hyunyoon Cho, Sukhyun Lim, YeonKyu Choi, Youngil Lim, Daesik Moon, Geuntae Park, Jin-Hun Jang, Kyungho Lee, Isak Hwang, Cheol Kim, Younghoon Son, Gil-Young Kang, Kiwon Park, Seungjun Lee, Su-Yeon Doo, Chang-Ho Shin, Byongwook Na, Ji-Suk Kwon, Kyung Ryun Kim, Hye-In Choi, Seouk-Kyu Choi, Soobong Chang, Wonil Bae, Hyuck-Joon Kwon, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee	22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.	ISSCC	2020	DBLP DOI BibTeX RDF
18	Shoji Nishimura, Haruo Yokota	QUILTS: Multidimensional Data Partitioning Framework Based on Query-Aware and Skew-Tolerant Space-Filling Curves.	SIGMOD Conference	2017	DBLP DOI BibTeX RDF
18	Sandipan Kundu, Erkan Alpman, Julia Hsin-Lin Lu, Hasnain Lakdawala, Jeyanandh Paramesh, Byunghoo Jung, Sarit Zur, Eshel Gordon	A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
18	Sandipan Kundu, Julia Hsin-Lin Lu, Erkan Alpman, Hasnain Lakdawala, Jeyanandh Paramesh, Byunghoo Jung, Sarit Zur, Eshel Gordon	A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN.	CICC	2014	DBLP DOI BibTeX RDF
18	Jihoon Son, Hyunsik Choi, Yon Dohn Chung	Skew-Tolerant Key Distribution for Load Balancing in MapReduce.	IEICE Trans. Inf. Syst.	2012	DBLP DOI BibTeX RDF
18	Keisuke Inoue, Mineo Kaneko	A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
18	Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad	All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs.	Integr.	2011	DBLP DOI BibTeX RDF
18	Yuichi Nakamura 0002	A design method for skew tolerant latch design.	APCCAS	2008	DBLP DOI BibTeX RDF
18	Bruce A. Wilson, Mario Blaum	Skew-Tolerant Gray Codes.	ISIT	2006	DBLP DOI BibTeX RDF
18	Pavel V. Petkov, Jim E. Conder, Friedel Gerfers	An infinite-skew tolerant delay locked loop.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Sungwook Kim, Gerald E. Sobelman	Digit-serial modular multiplication using skew-tolerant domino CMOS.	ICASSP	2001	DBLP DOI BibTeX RDF
18	Gunok Jung, Victoria Perepelitsa, Gerald E. Sobelman	Time borrowing in high-speed functional units using skew-tolerant domino circuits.	ISCAS	2000	DBLP DOI BibTeX RDF
18	Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim	A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
18	David L. Harris, Mark A. Horowitz	Skew-tolerant domino circuits.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
18	Mario Blaum, Jehoshua Bruck	Coding for skew-tolerant parallel asynchronous communications.	IEEE Trans. Inf. Theory	1993	DBLP DOI BibTeX RDF
12	Charbel J. Akl, Magdy A. Bayoumi	Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family.	ISQED	2008	DBLP DOI BibTeX RDF	circuit family, low-power, high-speed
12	Marius Bozga, Oded Maler, Stavros Tripakis	Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics.	CHARME	1999	DBLP DOI BibTeX RDF