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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 31 occurrences of 27 keywords
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Results
Found 13 publication records. Showing 13 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
31 | Janusz A. Brzozowski, Kaamran Raahemifar |
Testing C-elements is not elementary. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 150-159, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
C-elements testing, gate circuits, C-element, CMOS implementations, logic testing, logic tests, asynchronous circuits, fault location, stuck-at faults, speed-independence |
23 | Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet |
Verifying a Self-Timed Divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 146-158, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
model checking, refinement, asynchronous, hardware verification, timing verification, self-timed, speed-independence |
23 | Radu Negulescu |
Event-Driven Verification of Switch-Level Correctness Concerns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 1st International Conference on Application of Concurrency to System Design (ACSD '98), 23-26 March 1998, Fukushima, Japan, pp. 213-223, 1998, IEEE Computer Society, 0-8186-8350-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
switch-level, Verification, concurrency, safety, deadlock, asynchronous, event-driven, speed-independence, process spaces |
17 | Martin E. Bush, Mark B. Josephs |
Some limitations to speed-independence in asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), March 18-21, 1996, Aizu-Wakamatsu, Fukushima, Japan, pp. 104-111, 1996, IEEE Computer Society, 0-8186-7298-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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17 | Michael Kishinevsky, Jørgen Staunstrup |
Characterizing speed-independence of high-level designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1994, Salt Lake City, UT, USA, November 3-5, 1994, pp. 44-53, 1994, IEEE, 0-8186-6210-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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17 | Michael Kishinevsky, Jørgen Staunstrup |
Mechanized Verification of Speed-independence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPCD ![In: Theorem Provers in Circuit Design - Theory, Practice and Experience, Second International Conference, TPCD '94, Bad Herrenalb, Germany, September 26-28, 1994, Proceedings, pp. 146-164, 1994, Springer, 3-540-59047-1. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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14 | D. J. Kinniment |
An evaluation of asynchronous addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(1), pp. 137-140, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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12 | William B. Toms, David A. Edwards |
Efficient synthesis of speed-independent combinational logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1022-1026, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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12 | Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev |
Decomposition and technology mapping of speed-independent circuits using Boolean relations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9), pp. 1221-1236, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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12 | Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev |
Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 98-105, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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12 | Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev |
Decomposition and technology mapping of speed-independent circuits using Boolean relations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 220-227, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Boolean decomposition, decomposed logic sharing, design library, library matching, logic decomposition, logic resynthesis, signal insertion, two-input combinational gate, two-input sequential gate, optimization, technology mapping, circuit CAD, speed-independent circuits, netlist, complex gates, Boolean relations |
10 | Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev |
Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 240-253, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
combinational decomposition, sequential decomposition, monotonous cover, signal insertion, factorization, hazards, resynthesis, Speed-independent circuit |
8 | Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli |
Synthesis of hazard-free asynchronous circuits with bounded wire delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1), pp. 61-86, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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