Search results for "speed-independence"

Found 13 publication records. Showing 13 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Janusz A. Brzozowski, Kaamran Raahemifar	Testing C-elements is not elementary.	ASYNC	1995	DBLP DOI BibTeX RDF	C-elements testing, gate circuits, C-element, CMOS implementations, logic testing, logic tests, asynchronous circuits, fault location, stuck-at faults, speed-independence
23	Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet	Verifying a Self-Timed Divider.	ASYNC	1998	DBLP DOI BibTeX RDF	model checking, refinement, asynchronous, hardware verification, timing verification, self-timed, speed-independence
23	Radu Negulescu	Event-Driven Verification of Switch-Level Correctness Concerns.	ACSD	1998	DBLP DOI BibTeX RDF	switch-level, Verification, concurrency, safety, deadlock, asynchronous, event-driven, speed-independence, process spaces
17	Martin E. Bush, Mark B. Josephs	Some limitations to speed-independence in asynchronous circuits.	ASYNC	1996	DBLP DOI BibTeX RDF
17	Michael Kishinevsky, Jørgen Staunstrup	Characterizing speed-independence of high-level designs.	ASYNC	1994	DBLP DOI BibTeX RDF
17	Michael Kishinevsky, Jørgen Staunstrup	Mechanized Verification of Speed-independence.	TPCD	1994	DBLP DOI BibTeX RDF
14	D. J. Kinniment	An evaluation of asynchronous addition.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
12	William B. Toms, David A. Edwards	Efficient synthesis of speed-independent combinational logic circuits.	ASP-DAC	2005	DBLP DOI BibTeX RDF
12	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev	Decomposition and technology mapping of speed-independent circuits using Boolean relations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
12	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev	Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis.	ED&TC	1997	DBLP DOI BibTeX RDF
12	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev	Decomposition and technology mapping of speed-independent circuits using Boolean relations.	ICCAD	1997	DBLP DOI BibTeX RDF	Boolean decomposition, decomposed logic sharing, design library, library matching, logic decomposition, logic resynthesis, signal insertion, two-input combinational gate, two-input sequential gate, optimization, technology mapping, circuit CAD, speed-independent circuits, netlist, complex gates, Boolean relations
10	Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev	Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis.	ASYNC	1997	DBLP DOI BibTeX RDF	combinational decomposition, sequential decomposition, monotonous cover, signal insertion, factorization, hazards, resynthesis, Speed-independent circuit
8	Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli	Synthesis of hazard-free asynchronous circuits with bounded wire delays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF