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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 55 occurrences of 49 keywords
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Results
Found 38 publication records. Showing 38 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
53 | Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta 0001, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta |
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 261-266, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
common sub-expression elimination, dynamic CSE, parallelizing transformations, high-level synthesis |
29 | Jiun-In Guo, Jui-Cheng Yen |
An Efficient IDCT Processor Design for HDTV Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 147-155, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform (IDCT), adder-based implementation, common sub-expression sharing, HDTV, cyclic convolution |
29 | Kavish Seth, S. Srinivasan 0001 |
VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 435-440, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
2D-DWT/IDWT Hardware, Non-expansive symmetric Extension, Canonic Signed Digit Arithmetic, Sub-expression Sharing, Low Power |
29 | Xinan Tang, Rakesh Ghiya, Laurie J. Hendren, Guang R. Gao |
Heap Analysis and Optimizations for Threaded Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 14-25, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
threaded programs, traditional compiler optimizations, loop invariant removal, common sub-expression elimination, dynamically allocated data structures, heap pointer analyses, dependence testing, high quality code generation, EARTH-C compiler, generated multithreaded code, dynamic measurements, performance tradeoffs, optimizations, parallel programming, optimizing compilers, multithreaded architectures, multithreaded programs, heap analysis |
28 | Qiu-Zhong Wu, Yi-He Sun |
An Integrated CAD Tool for ASIC Implementation of Multiplierless FIR Filters with Common Sub-expression Elimination Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2005, September 22-23, 2005, New York Metropolitan Area, USA, pp. 67-72, 2005, IEEE Computer Society, 0-7803-9347-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Arash Arfaee, Ali Irturk, Nikolay Laptev, Farzan Fallah, Ryan Kastner |
Xquasher: a tool for efficient computation of multiple linear expressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 254-257, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
DSP transforms, common sub-expression elimination, linear expression, multiple constant multiplications, area optimization |
22 | Nitzan Weinberg, David Nagle |
Dynamic Elimination of Pointer-Expressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 12-18, 1998, pp. 142-147, 1998, IEEE Computer Society, 0-8186-8591-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
pointer-expression, sphinx, sub-expression, SPECint95, memory address, performance analysis, compiler, locality, speech recognition, dynamic, microprocessor, mpeg, cache memory, microarchitecture, jpeg, value, spatial, memory bandwidth, data reuse, temporal, pointer, conditional execution |
20 | J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, Mahmut T. Kandemir |
Address Code and Arithmetic Optimizations for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 619-624, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
address arithmetic optimization, array access to scalar access conversion, embedded systems, compiler optimizations, pointers |
14 | Bala Gurumurthy, Vasudev Raghavendra Bidarkar, David Broneske, Thilo Pionteck, Gunter Saake |
What Happens When Two Multi-Query Optimization Paradigms Combine? - A Hybrid Shared Sub-Expression (SSE) and Materialized View Reuse (MVR) Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS ![In: Advances in Databases and Information Systems - 27th European Conference, ADBIS 2023, Barcelona, Spain, September 4-7, 2023, Proceedings, pp. 74-87, 2023, Springer, 978-3-031-42913-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee |
A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1), pp. 130-140, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Ila Sharma, Anil Kumar 0001, Girish Kumar Singh 0002, Heung-No Lee |
Design of multiplierless cosine modulated filterbank using hybrid technique in sub-expression space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 2016 IEEE International Conference on Digital Signal Processing, DSP 2016, Beijing, China, October 16-18, 2016, pp. 360-364, 2016, IEEE, 978-1-5090-4165-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee |
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4), pp. 1071-1080, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Ayesha Khalid, Rajat Sen, Anupam Chattopadhyay |
SI-DFA: Sub-expression integrated Deterministic Finite Automata for Deep Packet Inspection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPSR ![In: IEEE 14th International Conference on High Performance Switching and Routing, HPSR 2013, Taipei, Taiwan, July 8-11, 2013, pp. 164-170, 2013, IEEE, 978-1-4673-4620-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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14 | Huong Ho, Valek Szwarc, Tad A. Kwasniewski |
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 61(3), pp. 353-365, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Muhammad Bilal 0001, Shahid Masud |
FIR filter implementation through Speculative Sub-Expression Sharing in image data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2010, 14-19 March 2010, Sheraton Dallas Hotel, Dallas, Texas, USA, pp. 1582-1585, 2010, IEEE, 978-1-4244-4296-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Sivaram Gopalakrishnan, Priyank Kalla |
Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, pp. 1452-1457, 2009, IEEE, 978-1-4244-3781-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Yuen-Hong Alvin Ho, Chi-Un Lei, Hing-Kit Kwan, Ngai Wong |
Optimal Common Sub-Expression Elimination Algorithm of Multiple Constant Multiplications with a Logic Depth Constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12), pp. 3568-3575, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Mohammed Javed Absar, Pol Marchal, Francky Catthoor |
Data-Access Optimization of Embedded Systems Through Selective Inlining Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2005, September 22-23, 2005, New York Metropolitan Area, USA, pp. 75-80, 2005, IEEE Computer Society, 0-7803-9347-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Hunsoo Choo, Khurram Muhammad, Kaushik Roy 0001 |
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10700-10705, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen |
Area-effective FIR filter design for multiplier-less implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 173-176, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Chandrashekhar A. Dhote, M. S. Ali |
Materialized View Selection in Data Warehousing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2-4 April 2007, Las Vegas, Nevada, USA, pp. 843-847, 2007, IEEE Computer Society, 978-0-7695-2776-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jun Cao, Ayush Goyal, Samuel P. Midkiff, James M. Caruthers |
An Optimizing Compiler for Parallel Chemistry Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-10, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Haifeng Zhou, Zhenghui Lin, Wei Cao |
Research on VHDL RTL Synthesis System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 99-103, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
VHDL RTL synthesis, ambiguous grammar, language level optimization, inference, formal semantics, parser |
7 | Arthur I. Baars, S. Doaitse Swierstra, Marcos Viera |
Typed transformations of typed abstract syntax. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TLDI ![In: Proceedings of TLDI'09: 2009 ACM SIGPLAN International Workshop on Types in Languages Design and Implementation, Savannah, GA, USA, January 24, 2009, pp. 15-26, 2009, ACM, 978-1-60558-420-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
typed transformations, type systems, meta-programming, gadt, common subexpression elimination |
7 | Shrutisagar Chandrasekaran, Abbes Amira |
High Performance FPGA Implementation of the Mersenne Twister. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 482-485, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
RC1000, FPGA, Mersenne Twister, Handel C |
7 | Oscar Gustafsson, Mikael Olofsson |
Complexity Reduction of Constant Matrix Computations over the Binary Field. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WAIFI ![In: Arithmetic of Finite Fields, First International Workshop, WAIFI 2007, Madrid, Spain, June 21-22, 2007, Proceedings, pp. 103-115, 2007, Springer, 978-3-540-73073-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
constant multiplication, low-complexity, binary field, Galois field arithmetic |
7 | François Pottier |
From ML type inference to stratified type inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFP ![In: Proceedings of the 10th ACM SIGPLAN International Conference on Functional Programming, ICFP 2005, Tallinn, Estonia, September 26-28, 2005, pp. 1, 2005, ACM, 1-59593-064-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
7 | Sumit Gupta, Rajesh K. Gupta 0001, Nikil D. Dutt, Alexandru Nicolau |
Coordinated parallelizing compiler optimizations and high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(4), pp. 441-470, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dynamic CSE, parallelizing transformations, presynthesis, embedded systems, high-level synthesis, Code motions, common subexpression elimination |
7 | Nalin Sidahao |
Optimized Field Programmable Gate Array Based Function Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 1184, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung |
Multiple Restricted Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 374-383, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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7 | Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen |
A power-aware IP core generator for the one-dimensional discrete Fourier transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 637-640, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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7 | P. W. Chandana Prasad, M. Maria Dominic, Ashutosh Kumar Singh |
Variable Order Verification Use of Logic Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICADL ![In: Digital Libraries: Technology and Management of Indigenous Knowledge for Global Access, 6th International Conference on Asian Digital Libraries, ICADL 2003, Kuala Lumpur, Malaysia, December 8-12, 2003, Proceedings, pp. 689, 2003, Springer, 3-540-20608-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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7 | Nicolas Boullis, Arnaud Tisserand |
Some Optimizations of Hardware Multiplication by Constant Matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, pp. 20-27, 2003, IEEE Computer Society, 0-7695-1894-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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7 | Kuang-Fu Cheng, Sau-Gee Chen |
A low-complexity correlation algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 301-304, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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7 | Jiun-In Guo |
A low cost 2-D inverse discrete cosine transform design for image compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 658-661, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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7 | Arthur T. G. Fuller, Behrouz Nowrouzian |
A novel technique for optimization over the canonical signed-digit number space using genetic algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 745-748, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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7 | Xuejun Du, Gary D. Hachtel, Bill Lin 0001, A. Richard Newton |
MUSE: a multilevel symbolic encoding algorithm for state assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(1), pp. 28-38, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
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7 | Vincent A. Busam, Donald E. Englund |
Optimization of expressions in Fortran. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 12(12), pp. 666-674, 1969. The full citation details ...](Pics/full.jpeg) |
1969 |
DBLP DOI BibTeX RDF |
DO loops, invariant calculations, optimization, compilation, compilers, FORTRAN, FORTRAN, register allocation, expressions, common subexpressions, subscripts |
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