Search results for "switchbox"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
85	Nobuo Funabiki, Seishi Nishikawa	A neural network model for multilayer topological via minimization in a switchbox.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
75	Jens Lienig	Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm Approach.	VLSI Design	1997	DBLP DOI BibTeX RDF	minimized crosstalk, interconnection routing, interconnection crosstalk, VLSI channel routing, VLSI switchbox routing, distributed workstation network, VLSI, VLSI design, parallel genetic algorithm
66	Stephan Hartmann 0003, Markus W. Schäffter, Andreas S. Schulz	Switchbox Routing in VLSI Design: Closing the Complexity Gap.	WG	1996	DBLP DOI BibTeX RDF
66	Tae Won Cho, Sam S. Pyo, J. Robert Heath	PARALLEX: a parallel approach to switchbox routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
66	Tong Gao, C. L. Liu 0001	Minimum crosstalk switchbox routing.	ICCAD	1994	DBLP DOI BibTeX RDF
66	Pierre-François Dubois, Alain Puissochet, Anne-Marie Tagant	A general and flexible switchbox router: CARIOCA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
66	Michael Kaufmann 0001	Allowing overlaps makes switchbox layouts nice.	SPDP	1990	DBLP DOI BibTeX RDF
66	James P. Cohoon, Patrick L. Heck	BEAVER: a computational-geometry-based tool for switchbox routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
66	Michael Kaufmann 0001, Kurt Mehlhorn	Routing Through a Generalized Switchbox.	ICALP	1985	DBLP DOI BibTeX RDF
57	Matthias F. M. Stallmann, Thomas A. Hughes, Wentai Liu	Unconstrained via minimization for topological multilayer routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
57	Steven T. Healey, William J. Kubitz	Abstract Routing of Logic Networks for Custom Module Generation.	DAC	1987	DBLP DOI BibTeX RDF
47	Sandip Das 0001, Susmita Sur-Kolay, Bhargab B. Bhattacharya	Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model.	VLSI Design	1998	DBLP DOI BibTeX RDF	nonslicible floorplan, switchbox, Manhattan-diagonal model, channel, VLSI routing
47	Masahiro Nagamatu, Shakeel Ismail, Torao Yanaru	Lagrangian method for wire routing of layout design.	ANNES	1995	DBLP DOI BibTeX RDF	wire routing, layout design, LSI layout design, continuous valued constrained optimization problem, continuous valued wires, dynamic equations, small switchbox routing problems, rip-up reroute maze router, neural nets, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, large scale integration, neurocomputing, Lagrangian method
47	Akinori Kanasugi, Takashi Shimayama, Naoshi Nakaya, Takeshi Iizuka	A Genetic Algorithm for Switchbox Routing Problem.	Rough Sets and Current Trends in Computing	1998	DBLP DOI BibTeX RDF
47	Sabih H. Gerez, Otto E. Herrmann	Switchbox routing by stepwise reshaping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
28	Hasan Arslan, Shantanu Dutt	An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	bump and refit paradigm, bumping cost, hop-based routing, switchbox, FPGAs, detailed routing, MST
28	Shantanu Dutt, Vinay Verma, Hasan Arslan	A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Bump-and-refit (B&R) paradigm, ECO (engineering change order), bumping cost, incremental routing, switchbox, field programmable gate arrays, dynamic programming, global routing, detailed routing
28	Tim Lackorzynski, Philipp Rietzsch, Stefan Köpsell	Switchbox - Low-latency Fail-safe Assurance of Availability in Industrial Environments.	ICIT	2020	DBLP DOI BibTeX RDF
28	Marzieh Morshedzadeh, Ali Jahanian 0001, Payam Pourashraf	Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage.	Integr.	2015	DBLP DOI BibTeX RDF
28	M. S. Sangeetha, N. M. Nandhitha	Impact of distance on the hotspot temperature in thermal image for condition monitoring of UPS switchbox.	Int. J. Adv. Intell. Paradigms	2015	DBLP DOI BibTeX RDF
28	Bahman Afsari, Elana J. Fertig, Donald Geman, Luigi Marchionni	switchBox: an R package for k-Top Scoring Pairs classifier development.	Bioinform.	2015	DBLP DOI BibTeX RDF
28	Matthew Mayhew, Radu Muresan	Integrated capacitor switchbox for security protection.	ISCAS	2012	DBLP DOI BibTeX RDF
28	Dávid Szeszlér	Additive Approximation for Layer Minimization of Manhattan Switchbox Routing.	Electron. Notes Discret. Math.	2010	DBLP DOI BibTeX RDF
28	Maolin Tang	A Cooperative Approach to Switchbox Routing.	Int. J. Comput. Their Appl.	2004	DBLP BibTeX RDF
28	Frank Schmiedle, Daniel Unruh, Bernd Becker 0001	Exact switchbox routing with search space reduction.	ISPD	2000	DBLP DOI BibTeX RDF
28	Stephan Hartmann 0003, Markus W. Schäffter, Andreas S. Schulz	Switchbox Routing in VLSI Design: Closing the Complexity Gap.	Theor. Comput. Sci.	1998	DBLP DOI BibTeX RDF
28	Jens Lienig, Krishnaiyan Thulasiraman	Gasbor: a Genetic Algorithm Approach for Solving the switchbox Routing Problem.	J. Circuits Syst. Comput.	1996	DBLP DOI BibTeX RDF
28	Endre Boros, András Recski, Ferenc Wettl	Unconstrained multilayer switchbox routing.	Ann. Oper. Res.	1995	DBLP DOI BibTeX RDF
28	Tong Gao, C. L. Liu 0001	Minimum crosstalk switchbox routing.	Integr.	1995	DBLP DOI BibTeX RDF
28	Xiaoyu Song	An efficient DM switchbox router.	Microprocess. Microprogramming	1994	DBLP DOI BibTeX RDF
28	Jens Lienig, Krishnaiyan Thulasiraman	GASBOR: A Genetic Algorithm for Switchbox Routing in Integrated Circuits.	Evo Workshops	1994	DBLP DOI BibTeX RDF
28	Jon Hamkins, Donna J. Brown	Switchbox routing with movable terminals.	Great Lakes Symposium on VLSI	1993	DBLP DOI BibTeX RDF
28	Tae Won Cho, Sam S. Pyo, J. Robert Heath	A new conflict resolving switchbox router.	Great Lakes Symposium on VLSI	1992	DBLP DOI BibTeX RDF
28	Yang Cai 0003, Martin D. F. Wong	Channel/switchbox definition for VLSI building-block layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
28	M. Starkey, Tony M. Carter	Switchbox Routing by Pattern Matching.	VLSI	1991	DBLP BibTeX RDF
28	S. Miriyala, Jahangir A. Hashmi, Naveed A. Sherwani	Switchbox Steiner Tree Problem in Presence of Obstacles.	ICCAD	1991	DBLP DOI BibTeX RDF
28	Majid Sarrafzadeh	Area Minimization in a Three-Sided Switchbox by Sliding the Modules.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF
28	Yang Cai 0003, D. F. Wong 0001	A Channel/Switchbox Definition Algorithm for Building-Block Layout.	DAC	1990	DBLP DOI BibTeX RDF
28	Kok-Phuang Tan, Tiow Seng Tan	Switchbox routing using score function.	Integr.	1989	DBLP DOI BibTeX RDF
28	Michael Kaufmann 0001, Kurt Mehlhorn	Routing Through a Generalized Switchbox.	J. Algorithms	1986	DBLP DOI BibTeX RDF
28	Gordon T. Hamachi, John K. Ousterhout	A switchbox router with obstacle avoidance.	DAC	1984	DBLP BibTeX RDF
19	Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin	Physical Design of FPGA Interconnect to Prevent Information Leakage.	ARC	2008	DBLP DOI BibTeX RDF
19	Sandip Das 0001, Susmita Sur-Kolay, Bhargab B. Bhattacharya	Manhattan-diagonal routing in channels and switchboxes.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Manhattan routing, channel density, diagonal wires
19	Le-Chin Eugene Liu, Hsiao-Ping Tseng, Carl Sechen	Chip-level area routing.	ISPD	1998	DBLP DOI BibTeX RDF
19	Jin-Tai Yan, Pei-Yung Hsiao	Minimizing the number of switchboxes for region definition and ordering assignment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
19	Tai-Tsung Ho, S. Sitharama Iyengar, Si-Qing Zheng	A general greedy channel routing algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
19	Godfried M. Swinkels, Louis J. Hafer	Schematic generation with an expert system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
19	Bryan Preas	Channel routing with non-terminal doglegs.	EURO-DAC	1990	DBLP DOI BibTeX RDF
19	Fillia Makedon, Malgorzata Marek-Sadowska	Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic.	ICCAL	1989	DBLP DOI BibTeX RDF
19	Mehdi R. Zargham	Parallel Channel Routing.	DAC	1988	DBLP BibTeX RDF