Search results for "tapered-buffer"

Found 14 publication records. Showing 14 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
117	Brian S. Cherkauer, Eby G. Friedman	A unified design methodology for CMOS tapered buffers.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
83	S. R. Vemuru	Effects of simultaneous switching noise on the tapered buffer design.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
67	Hua Wang, Francky Catthoor, Miguel Miranda, Wim Dehaene	Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	CMOS buffer, Low power design, Trade-offs
58	Gerard Villar, Eduard Alarcón, Jordi Madrenas, Francesc Guinjoan, Alberto Poveda	Energy optimization of tapered buffers for CMOS on-chip switching power converters.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
42	Fei Qiao, Huazhong Yang, Gang Huang, Hui Wang 0004	Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	low-swing interface, differential signaling, tapered-buffer, interconnect, asynchronous circuit, low power circuit
42	Hua Wang, Miguel Miranda, Antonis Papanikolaou, Francky Catthoor, Wim Dehaene	Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
27	Song Liu, Seda Ogrenci Memik, Yehea I. Ismail	A Comprehensive Tapered buffer optimization algorithm for unified design metrics.	ISCAS	2011	DBLP DOI BibTeX RDF
27	João Navarro Jr., Wilhelmus A. M. Van Noije	CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
27	Jso-Sun Choi, Kwyro Lee	Design of CMOS tapered buffer for minimum power-delay product.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
27	Nils Hedenstiema, Kjell O. Jeppson	Comments on the optimum CMOS tapered buffer problem.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
27	Laszlo Gal	Reply to "Comments on the optimum CMOS tapered buffer problem".	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
27	Brian S. Cherkauer, Eby G. Friedman	Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design.	ISCAS	1994	DBLP DOI BibTeX RDF
25	Bill Pontikakis, François R. Boyer, Yvon Savaria	A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Chang Woo Kang, Soroush Abbaspour, Massoud Pedram	Buffer sizing for minimum energy-delay product by using an approximating polynomial.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	short circuit energy, buffer sizing, polynomial approximation