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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 7 occurrences of 7 keywords
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Results
Found 14 publication records. Showing 14 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
117 | Brian S. Cherkauer, Eby G. Friedman |
A unified design methodology for CMOS tapered buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(1), pp. 99-111, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
83 | S. R. Vemuru |
Effects of simultaneous switching noise on the tapered buffer design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(3), pp. 290-300, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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67 | Hua Wang, Francky Catthoor, Miguel Miranda, Wim Dehaene |
Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(2), pp. 193-210, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CMOS buffer, Low power design, Trade-offs |
58 | Gerard Villar, Eduard Alarcón, Jordi Madrenas, Francesc Guinjoan, Alberto Poveda |
Energy optimization of tapered buffers for CMOS on-chip switching power converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4453-4456, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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42 | Fei Qiao, Huazhong Yang, Gang Huang, Hui Wang 0004 |
Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(7), pp. 975-984, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low-swing interface, differential signaling, tapered-buffer, interconnect, asynchronous circuit, low power circuit |
42 | Hua Wang, Miguel Miranda, Antonis Papanikolaou, Francky Catthoor, Wim Dehaene |
Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(10), pp. 1127-1135, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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27 | Song Liu, Seda Ogrenci Memik, Yehea I. Ismail |
A Comprehensive Tapered buffer optimization algorithm for unified design metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 2277-2280, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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27 | João Navarro Jr., Wilhelmus A. M. Van Noije |
CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 89-94, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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27 | Jso-Sun Choi, Kwyro Lee |
Design of CMOS tapered buffer for minimum power-delay product. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 29(9), pp. 1142-1145, September 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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27 | Nils Hedenstiema, Kjell O. Jeppson |
Comments on the optimum CMOS tapered buffer problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 29(2), pp. 155-158, February 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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27 | Laszlo Gal |
Reply to "Comments on the optimum CMOS tapered buffer problem". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 29(2), pp. 158-159, February 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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27 | Brian S. Cherkauer, Eby G. Friedman |
Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, pp. 111-114, 1994, IEEE, 0-7803-1916-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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25 | Bill Pontikakis, François R. Boyer, Yvon Savaria |
A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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21 | Chang Woo Kang, Soroush Abbaspour, Massoud Pedram |
Buffer sizing for minimum energy-delay product by using an approximating polynomial. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 112-115, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
short circuit energy, buffer sizing, polynomial approximation |
Displaying result #1 - #14 of 14 (100 per page; Change: )
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