Search results for "tensilica"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
39	Jens Karrenbauer, Lukas Gerlach 0001, Guillermo Payá Vayá, Holger Blume	Design Space Exploration Framework for Tensilica-Based Digital Audio Processors in Hearing Aids.	MOCAST	2020	DBLP DOI BibTeX RDF
39	Anirudh Ingole, Vanita Agarwal	Instruction Set Design for Elementary Set in Tensilica Xtensa.	ICCCNT	2019	DBLP DOI BibTeX RDF
39	D. R. Vasanthi, R. Anusha, B. K. Vinay	Implementation of Robust Compression Technique Using LZ77 Algorithm on Tensilica's Xtensa Processor.	ICIT	2016	DBLP DOI BibTeX RDF
39		Tensilica.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
36	Newton Cheung, Jörg Henkel, Sri Parameswaran	Rapid Configuration and Instruction Selection for an ASIP: A Case Study.	DATE	2003	DBLP DOI BibTeX RDF
29	Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	Understanding sources of inefficiency in general-purpose chips.	ISCA	2010	DBLP DOI BibTeX RDF	tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance
29	Krutartha Patel, Sri Parameswaran	LOCS: a low overhead profiler-driven design flow for security of MPSoCs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	tensilica, architecture, mpsoc, execution profile, code injection
29	Krutartha Patel, Sri Parameswaran	SHIELD: a software hardware design methodology for security and reliability of MPSoCs.	DAC	2008	DBLP DOI BibTeX RDF	bit flips, tensilica, architecture, multiprocessors, code injection
29	Krutartha Patel, Sridevan Parameswaran, Seng Lin Shee	Ensuring secure program execution in multiprocessor embedded systems: a case study.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	embedded system processors, tensilica, security, multiprocessors, code injection attacks
18	Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz	Using a configurable processor generator for computer architecture prototyping.	MICRO	2009	DBLP DOI BibTeX RDF	computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design
18	Marghoob Mohiyuddin, Mark Murphy, Leonid Oliker, John Shalf, John Wawrzynek, Samuel Williams 0001	A design methodology for domain-optimized power-efficient supercomputing.	SC	2009	DBLP DOI BibTeX RDF
18	Seng Lin Shee, Andrea Erdos, Sri Parameswaran	Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	design, architecture, multiprocessor, SoC, pipelines, ASIPs, heterogeneous system
18	Najwa Aaraj, Anand Raghunathan, Niraj K. Jha	Analysis and design of a hardware/software trusted platform module for embedded systems.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	embedded systems, multiprocessor systems, Custom instructions
18	Kwang-Ting (Tim) Cheng	From the EIC.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	Chris Rowen, runtime power monitoring, NoC, hybrid approach, simultaneous switching noise, RFIC
18	Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois	Acceleration of a 3D target tracking algorithm using an application specific instruction set processor.	ICCD	2008	DBLP DOI BibTeX RDF
18	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song 0002, Satoshi Goto	Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration.	ISQED	2008	DBLP DOI BibTeX RDF
18	Najwa Aaraj, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
18	Nachiketh R. Potlapally, Srivaths Ravi 0001, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha	Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
18	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
18	Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici	DATE 07 workshop on diagnostic services in NoCs.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	diagnostic services, DATE 2007, network on chip, NoC
18	Seng Lin Shee, Sri Parameswaran	Design Methodology for Pipelined Heterogeneous Multiprocessor System.	DAC	2007	DBLP DOI BibTeX RDF
18	Laura Pozzi, Kubilay Atasu, Paolo Ienne	Exact and approximate algorithms for the extension of embedded processor instruction sets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
18	Najwa Aaraj, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Architectures for efficient face authentication in embedded systems.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
18	Divya Arora, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha	Architectural support for safe software execution on embedded processors.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	type safety, memory safety, extensible processors
18	Seng Lin Shee, Andrea Erdos, Sri Parameswaran	Heterogeneous multiprocessor implementations for JPEG: : a case study.	CODES+ISSS	2006	DBLP DOI BibTeX RDF
18	Grant Martin	Recent Developments in Configurable and Extensible Processors.	ASAP	2006	DBLP DOI BibTeX RDF
18	Nachiketh R. Potlapally, Srivaths Ravi 0001, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha	Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.	VLSI Design	2006	DBLP DOI BibTeX RDF	Performance, Embedded Systems, Security Protocols, Configurability, Extensibility, Embedded Processors, IPSec, Embedded Security
18	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.	VLSI Design	2006	DBLP DOI BibTeX RDF
18	Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre	Application specific instruction-set processor generation for video processing based on loop optimization.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
18	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.	VLSI Design	2005	DBLP DOI BibTeX RDF
18	Sadik Ezer, Scott Johnson	Smart diagnostics for configurable processor verification.	DAC	2005	DBLP DOI BibTeX RDF	embedded test-bench control, coverage, functional verification, diagnostics, configurable processors
18	Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A hybrid energy-estimation technique for extensible processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
18	Dan Hillman	Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm.	DATE	2004	DBLP DOI BibTeX RDF
18	Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Energy Estimation for Extensible Processors.	DATE	2003	DBLP DOI BibTeX RDF
18	Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli	Automatic Instruction Set Extension and Utilization for Embedded Processors.	ASAP	2003	DBLP DOI BibTeX RDF
18	Li Chen, Srivaths Ravi 0001, Anand Raghunathan, Sujit Dey	A scalable software-based self-test methodology for programmable processors.	DAC	2003	DBLP DOI BibTeX RDF	scalability, microprocessor, at-speed test, software-based self-test, test program, manufacturing test
18	Hiroshi Tsutsui, Takahiko Masuzaki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura	High speed JPEG2000 encoder by configurable processor.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
18	Gülbin Ezer	Xtensa with User Defined DSP Coprocessor Microarchitectures.	ICCD	2000	DBLP DOI BibTeX RDF