Search results for "testbenches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
83	Renate Henftling, Wolfgang Ecker, Andreas Zinn, Martin Zambaldi, Matthias Bauer 0003	An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures.	IPDPS	2003	DBLP DOI BibTeX RDF	re-configurable architecture, hardware testbenches, acceleration of functional simulation, coarse-granular, fine-granular
82	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL.	DATE	2006	DBLP DOI BibTeX RDF
69	Darren Galpin, Cormac Driver, Siobhán Clarke	Modelling hardware verification concerns specified in the e language: an experience report.	AOSD	2009	DBLP DOI BibTeX RDF	theme/uml, hardware verification, aspect-oriented modelling, e
69	Stanislaw Deniziak, Krzysztof Sapiecha	High Level Testbench Generation for VHDL Models.	ECBS	1999	DBLP DOI BibTeX RDF	simulation, VHDL, testbench
65	Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang	A PD-based methodology to enhance efficiency in testbenches with random stimulation.	SBCCI	2009	DBLP DOI BibTeX RDF	parameter domains, system-on-chip, design methodologies, functional verification, coverage analysis
65	Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi	Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification.	DSD	2008	DBLP DOI BibTeX RDF
48	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	TBV, Model checking, fault models, functional verification, TLM
48	David W. Matula, Lee D. McFearin	A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division.	DATE	2006	DBLP DOI BibTeX RDF
48	Rohit Jindal, Kshitiz Jain	Verification of Transaction-Level SystemC models using RTL Testbenches.	MEMOCODE	2003	DBLP DOI BibTeX RDF
35	Görschwin Fey, Rolf Drechsler	Improving simulation-based verification by means of formal methods.	ASP-DAC	2004	DBLP DOI BibTeX RDF
35	S. Regimbal, Yvon Savaria, Guy Bois	Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models.	IWSOC	2004	DBLP DOI BibTeX RDF
31	Kelly D. Larson	Translation of an existing VMM-based SystemVerilog testbench to OVM.	DAC	2008	DBLP DOI BibTeX RDF	OVM, VMM, testbenches, SystemVerilog
31	F. Sforza, L. Battú, M. Brunelli, A. Castelnuovo, M. Magnaghi	A "Design for Verification" Methodology.	ISQED	2001	DBLP DOI BibTeX RDF	IP re-use, simulation, prototyping, emulation, functional verification, testbenches
30	Mariusz Jankowski, Jacek Nazdrowicz, Piotr Zajac, Piotr Amrozik, Michal Szermer, Cezary Maj, Grzegorz Jablonski	Observation of Readout Temperature Dependence and Its Variability for the MEMS and ASIC System Specimens and Their PCB Testbenches.	MIXDES	2022	DBLP DOI BibTeX RDF
30	Michael F. Dossis	Rapid, Formal Verification with Automated and Executable, Cycle-accurate simulators, and Generated Testbenches.	PCI	2020	DBLP DOI BibTeX RDF
30	Chan Kim, In San Jeon, Young-Su Kwon, Hyun-Mi Kim, Chun-Gi Lyuh, Yong Cheol Peter Cho, Jeongmin Yang, Jaehoon Chung, Kyoung-Seon Shin, Jinho Han, Min-Seok Choi	Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator.	ICCE-Berlin	2019	DBLP DOI BibTeX RDF
30	Varun Sharma, Naif Tarafdar, Paul Chow	Sonar: Writing Testbenches through Python.	FCCM	2019	DBLP DOI BibTeX RDF
30	Marcelo Sousa, Alper Sen 0001	Generation of TLM testbenches using mutation testing.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
30	Wolfgang Müller 0003, Wolfgang Ecker	Testbenches for advanced TLM verification.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
30	Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo	Applying verification intention for design customization via property mining under constrained testbenches.	ICCD	2011	DBLP DOI BibTeX RDF
30	Wolfgang Müller 0003, Alexander Bol, Alexander Krupp, Ola Lundkvist	Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems.	DIPES/BICC	2010	DBLP DOI BibTeX RDF
30	Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Sara Vinco	Correct-by-construction generation of device drivers based on RTL testbenches.	DATE	2009	DBLP DOI BibTeX RDF
30	Martin Oberkönig, Martin Schickel, Hans Eveking	Quantitative Qualitätsaussagen über Testbenches mittels formaler Eigenschaften.	MBMV	2009	DBLP BibTeX RDF
30	Bhaskar Pal, Ansuman Banerjee, Arnab Sinha, Pallab Dasgupta	Accelerating Assertion Coverage With Adaptive Testbenches.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
30	Avi Ziv, Chris Wilson, Adnan Hamid, Joerg Grosse	Special session - What's so intelligent about testbenches?	HLDVT	2008	DBLP DOI BibTeX RDF
30	Cássio L. Rodrigues, Fábio Jorge Almeida Morais, Leandro Max L. Silva, Karina R. G. da Silva, Jorge C. A. de Figueiredo, Dalton Dario Serey Guerrero, Elmar U. K. Melcher	Functional verification methodology using Hierarchical Coloured Petri Nets-based testbenches.	SMC	2008	DBLP DOI BibTeX RDF
30	Alex Wakefield, Bassam Jamil Mohd	Constructing reusable testbenches.	HLDVT	2002	DBLP DOI BibTeX RDF
30	Markus Schütz	How to efficiently build VHDL testbenches.	EURO-DAC	1995	DBLP DOI BibTeX RDF
17	Marcelo Daniel Berejuck, César Albenes Zeferino	Adding mechanisms for QoS to a network-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	FPGA, systems-on-chip, networks-on-chip
17	Jamie Cullen	Evolving common LISP programs in a linear-genotype evolutionary computation system.	GEC Summit	2009	DBLP DOI BibTeX RDF	evolutionary meta compilation, evolutionary meta programming, artificial intelligence, genetic programming, evolutionary computation, grammatical evolution
17	Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui Chang, Sy-Yen Kuo	Enhancing bug hunting using high-level symbolic simulation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	bughunter, design for verification, symbolic simulation
17	J. P. Grossman, Cliff Young, Joseph A. Bank, Kenneth M. Mackenzie, Doug Ierardi, John K. Salmon, Ron O. Dror, David E. Shaw	Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	Anton, simulation, embedded software, special-purpose hardware
17	Sangeetha Sudhakrishnan, Liying Su, Jose Renau	Processor Verification with hwBugHunt.	ISQED	2008	DBLP DOI BibTeX RDF
17	Ioannis Mavroidis, Ioannis Papaefstathiou	Efficient testbench code synthesis for a hardware emulator system.	DATE	2007	DBLP DOI BibTeX RDF
17	Adrian E. Seigler, Gary A. Van Huben, Hari Mony	Formal Verification of Partial Good Self-Test Fencing Structures.	FMCAD	2007	DBLP DOI BibTeX RDF	fencing, formal verification, self test
17	Claas Cornelius, Frank Grassert, Siegmar Koppe, Dirk Timmermann	Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques.	VLSI Design	2007	DBLP DOI BibTeX RDF
17	Frederic Doucet, Ingolf Krüger, Rajesh K. Gupta 0001, R. K. Shyamasundar	Compositional interaction specifications for SystemC.	MEMOCODE	2006	DBLP DOI BibTeX RDF
17	Wolfgang Mueller, Yves Vanderperren	UML and model-driven development for SoC design.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	simulation, UML, SoC, tools, SystemC, UML profiles, ESL design
17	Tilman Glökler, Jason Baumgartner, Devi Shanmugam, A. E. (Rick) Seigler, Gary A. Van Huben, Barinjato Ramanandray, Hari Mony, Paul Roessler	Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning.	FMCAD	2006	DBLP DOI BibTeX RDF
17	Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil	Synthesis of synchronous assertions with guarded atomic actions.	MEMOCODE	2005	DBLP DOI BibTeX RDF
17	Charles H.-P. Wen, Li-C. Wang	Simulation Data Mining for Functional Test Pattern Justification.	MTV	2005	DBLP DOI BibTeX RDF
17	Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso	Is methodology the highway out of verification hell?	DAC	2005	DBLP DOI BibTeX RDF	verification, formal verification, methodology, assertions
17	Martin Zambaldi, Wolfgang Ecker, Renate Henftling, Matthias Bauer 0003	A Layered Adaptive Verification Platform for Simulation, Test, and Emulation.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
17	Young-Il Kim, Chong-Min Kyung	TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
17	Bita Gorjiara, Pai H. Chou, Nader Bagherzadeh, Mehrdad Reshadi, David W. Jensen	Fast and efficient voltage scheduling by evolutionary slack distribution.	ASP-DAC	2004	DBLP DOI BibTeX RDF
17	Haihua Shen, Yunji Chen, Jing Huang	EmGen: An Automatic Test-Program Generation Tool for Embedded IP Cores.	ICESS	2004	DBLP DOI BibTeX RDF
17	Soheil Ghiasi, Elaheh Bozorgzadeh, Siddharth Choudhuri, Majid Sarrafzadeh	A unified theory of timing budget management.	ICCAD	2004	DBLP DOI BibTeX RDF
17	Renate Henftling, Andreas Zinn, Matthias Bauer 0003, Wolfgang Ecker, Martin Zambaldi	Platform-Based Testbench Generation.	DATE	2003	DBLP DOI BibTeX RDF
17	Rajesh K. Gupta 0001, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi	Formal verification - prove it or pitch it.	DAC	2003	DBLP DOI BibTeX RDF
17	Brad L. Hutchings, Brent E. Nelson	Unifying simulation and execution in a design environment for FPGA systems.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
17	Neal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas	Modeling and evaluation of hardware/software designs.	CODES	2001	DBLP DOI BibTeX RDF	computer system modeling and simulation, hardware/software codesign, digital system design
17	Kazutoshi Kobayashi, Hidetoshi Onodera	ST: PERL package for simulation and test environment.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
17	Andrew Stone, Elias S. Manolakos	DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
17	Wei-Chung Cheng, Massoud Pedram	Power-optimal encoding for DRAM address bus (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
17	Brad L. Hutchings, Brent E. Nelson	Using general-purpose programming languages for FPGA design.	DAC	2000	DBLP DOI BibTeX RDF