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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 48 occurrences of 38 keywords
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Results
Found 55 publication records. Showing 55 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
83 | Renate Henftling, Wolfgang Ecker, Andreas Zinn, Martin Zambaldi, Matthias Bauer 0003 |
An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 187, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
re-configurable architecture, hardware testbenches, acceleration of functional simulation, coarse-granular, fine-granular |
82 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli |
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1007-1012, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
69 | Darren Galpin, Cormac Driver, Siobhán Clarke |
Modelling hardware verification concerns specified in the e language: an experience report. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AOSD ![In: Proceedings of the 8th International Conference on Aspect-Oriented Software Development, AOSD 2009, Charlottesville, Virginia, USA, March 2-6, 2009, pp. 207-212, 2009, ACM, 978-1-60558-442-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
theme/uml, hardware verification, aspect-oriented modelling, e |
69 | Stanislaw Deniziak, Krzysztof Sapiecha |
High Level Testbench Generation for VHDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 6th Symposium on Engineering of Computer-Based Systems (ECBS '99), 7-12 March 1999, Nashville, TN, USA. IEEE Computer Society, 1999, pp. 146-151, 1999, IEEE Computer Society, 0-7695-0028-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
simulation, VHDL, testbench |
65 | Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang |
A PD-based methodology to enhance efficiency in testbenches with random stimulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
parameter domains, system-on-chip, design methodologies, functional verification, coverage analysis |
65 | Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi |
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 714-720, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
48 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli |
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(3), pp. 47:1-47:22, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
TBV, Model checking, fault models, functional verification, TLM |
48 | David W. Matula, Lee D. McFearin |
A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1134-1138, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Rohit Jindal, Kshitiz Jain |
Verification of Transaction-Level SystemC models using RTL Testbenches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 24-26 June 2003, Mont Saint-Michel, France, Proceedings, pp. 199-203, 2003, IEEE Computer Society, 0-7695-1923-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Görschwin Fey, Rolf Drechsler |
Improving simulation-based verification by means of formal methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 640-643, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | S. Regimbal, Yvon Savaria, Guy Bois |
Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada, pp. 87-92, 2004, IEEE Computer Society, 0-7695-2182-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Kelly D. Larson |
Translation of an existing VMM-based SystemVerilog testbench to OVM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 237, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
OVM, VMM, testbenches, SystemVerilog |
31 | F. Sforza, L. Battú, M. Brunelli, A. Castelnuovo, M. Magnaghi |
A "Design for Verification" Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 50-55, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
IP re-use, simulation, prototyping, emulation, functional verification, testbenches |
30 | Mariusz Jankowski, Jacek Nazdrowicz, Piotr Zajac, Piotr Amrozik, Michal Szermer, Cezary Maj, Grzegorz Jablonski |
Observation of Readout Temperature Dependence and Its Variability for the MEMS and ASIC System Specimens and Their PCB Testbenches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: 29th International Conference on Mixed Design of Integrated Circuits and System, MIXDES 2022, Wrocław, Poland, June 23-24, 2022, pp. 110-115, 2022, IEEE, 978-83-63578-22-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
30 | Michael F. Dossis |
Rapid, Formal Verification with Automated and Executable, Cycle-accurate simulators, and Generated Testbenches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PCI ![In: PCI 2020: 24th Pan-Hellenic Conference on Informatics, Athens, Greece, 20-22 November, 2020, pp. 144-147, 2020, ACM, 978-1-4503-8897-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
30 | Chan Kim, In San Jeon, Young-Su Kwon, Hyun-Mi Kim, Chun-Gi Lyuh, Yong Cheol Peter Cho, Jeongmin Yang, Jaehoon Chung, Kyoung-Seon Shin, Jinho Han, Min-Seok Choi |
Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE-Berlin ![In: 9th IEEE International Conference on Consumer Electronics, ICCE-Berlin 2019, Berlin, Germany, September 8-11, 2019, pp. 242-247, 2019, IEEE, 978-1-7281-2745-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
30 | Varun Sharma, Naif Tarafdar, Paul Chow |
Sonar: Writing Testbenches through Python. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019, San Diego, CA, USA, April 28 - May 1, 2019, pp. 311, 2019, IEEE, 978-1-7281-1131-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
30 | Marcelo Sousa, Alper Sen 0001 |
Generation of TLM testbenches using mutation testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2012, part of ESWeek '12 Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012, pp. 323-332, 2012, ACM, 978-1-4503-1426-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
30 | Wolfgang Müller 0003, Wolfgang Ecker |
Testbenches for advanced TLM verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2012, part of ESWeek '12 Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012, pp. 305-306, 2012, ACM, 978-1-4503-1426-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
30 | Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo |
Applying verification intention for design customization via property mining under constrained testbenches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011, pp. 84-89, 2011, IEEE Computer Society, 978-1-4577-1953-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
30 | Wolfgang Müller 0003, Alexander Bol, Alexander Krupp, Ola Lundkvist |
Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DIPES/BICC ![In: Distributed, Parallel and Biologically Inspired Systems - 7th IFIP TC 10 Working Conference, DIPES 2010 and 3rd IFIP TC 10 International Conference, BICC 2010, Held as Part of WCC 2010, Brisbane, Australia, September 20-23, 2010. Proceedings, pp. 78-89, 2010, Springer, 978-3-642-15233-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
30 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Sara Vinco |
Correct-by-construction generation of device drivers based on RTL testbenches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, pp. 1500-1505, 2009, IEEE, 978-1-4244-3781-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Martin Oberkönig, Martin Schickel, Hans Eveking |
Quantitative Qualitätsaussagen über Testbenches mittels formaler Eigenschaften. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Berlin, Germany, March 2-4, 2009, pp. 17-26, 2009, Universitätsbibliothek Berlin, Germany. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
30 | Bhaskar Pal, Ansuman Banerjee, Arnab Sinha, Pallab Dasgupta |
Accelerating Assertion Coverage With Adaptive Testbenches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5), pp. 967-972, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Avi Ziv, Chris Wilson, Adnan Hamid, Joerg Grosse |
Special session - What's so intelligent about testbenches? ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: IEEE International High Level Design Validation and Test Workshop, HLDVT 2008, Incline Village, NV, USA, November 19-21, 2008, pp. 141-142, 2008, IEEE Computer Society, 978-1-4244-2922-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Cássio L. Rodrigues, Fábio Jorge Almeida Morais, Leandro Max L. Silva, Karina R. G. da Silva, Jorge C. A. de Figueiredo, Dalton Dario Serey Guerrero, Elmar U. K. Melcher |
Functional verification methodology using Hierarchical Coloured Petri Nets-based testbenches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, Singapore, 12-15 October 2008, pp. 2093-2098, 2008, IEEE, 978-1-4244-2383-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Alex Wakefield, Bassam Jamil Mohd |
Constructing reusable testbenches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Seventh IEEE International High-Level Design Validation and Test Workshop 2002, Cannes, France, October 27-29, 2002, pp. 151-155, 2002, IEEE Computer Society, 0-7803-7655-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Markus Schütz |
How to efficiently build VHDL testbenches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995, pp. 554-559, 1995, IEEE Computer Society, 0-8186-7156-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Marcelo Daniel Berejuck, César Albenes Zeferino |
Adding mechanisms for QoS to a network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, systems-on-chip, networks-on-chip |
17 | Jamie Cullen |
Evolving common LISP programs in a linear-genotype evolutionary computation system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GEC Summit ![In: Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation, GEC Summit 2009, Shanghai, China, June 12-14, 2009, pp. 75-80, 2009, ACM, 978-1-60558-326-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
evolutionary meta compilation, evolutionary meta programming, artificial intelligence, genetic programming, evolutionary computation, grammatical evolution |
17 | Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui Chang, Sy-Yen Kuo |
Enhancing bug hunting using high-level symbolic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 417-420, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bughunter, design for verification, symbolic simulation |
17 | J. P. Grossman, Cliff Young, Joseph A. Bank, Kenneth M. Mackenzie, Doug Ierardi, John K. Salmon, Ron O. Dror, David E. Shaw |
Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 125-130, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Anton, simulation, embedded software, special-purpose hardware |
17 | Sangeetha Sudhakrishnan, Liying Su, Jose Renau |
Processor Verification with hwBugHunt. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 224-229, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Ioannis Mavroidis, Ioannis Papaefstathiou |
Efficient testbench code synthesis for a hardware emulator system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 888-893, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Adrian E. Seigler, Gary A. Van Huben, Hari Mony |
Formal Verification of Partial Good Self-Test Fencing Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 7th International Conference, FMCAD 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings, pp. 188-191, 2007, IEEE Computer Society, 0-7695-3023-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fencing, formal verification, self test |
17 | Claas Cornelius, Frank Grassert, Siegmar Koppe, Dirk Timmermann |
Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 330-338, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Frederic Doucet, Ingolf Krüger, Rajesh K. Gupta 0001, R. K. Shyamasundar |
Compositional interaction specifications for SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 27-29 July 2006, Embassy Suites, Napa, California, USA, pp. 201, 2006, IEEE Computer Society, 1-4244-0421-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Wolfgang Mueller, Yves Vanderperren |
UML and model-driven development for SoC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 1, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
simulation, UML, SoC, tools, SystemC, UML profiles, ESL design |
17 | Tilman Glökler, Jason Baumgartner, Devi Shanmugam, A. E. (Rick) Seigler, Gary A. Van Huben, Barinjato Ramanandray, Hari Mony, Paul Roessler |
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 6th International Conference, FMCAD 2006, San Jose, California, USA, November 12-16, 2006, Proceedings, pp. 3-10, 2006, IEEE Computer Society, 0-7695-2707-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil |
Synthesis of synchronous assertions with guarded atomic actions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 11-14 July 2005, Verona, Italy, Proceedings, pp. 15-24, 2005, IEEE Computer Society, 0-7803-9227-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Charles H.-P. Wen, Li-C. Wang |
Simulation Data Mining for Functional Test Pattern Justification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 76-83, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso |
Is methodology the highway out of verification hell? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 521-522, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
verification, formal verification, methodology, assertions |
17 | Martin Zambaldi, Wolfgang Ecker, Renate Henftling, Matthias Bauer 0003 |
A Layered Adaptive Verification Platform for Simulation, Test, and Emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(6), pp. 464-471, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Young-Il Kim, Chong-Min Kyung |
TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(6), pp. 484-493, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Bita Gorjiara, Pai H. Chou, Nader Bagherzadeh, Mehrdad Reshadi, David W. Jensen |
Fast and efficient voltage scheduling by evolutionary slack distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 659-662, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Haihua Shen, Yunji Chen, Jing Huang |
EmGen: An Automatic Test-Program Generation Tool for Embedded IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, First International Conference, ICESS 2004, Hangzhou, China, December 9-10, 2004, Revised Selected Papers, pp. 528-535, 2004, Springer, 3-540-28128-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Soheil Ghiasi, Elaheh Bozorgzadeh, Siddharth Choudhuri, Majid Sarrafzadeh |
A unified theory of timing budget management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 653-659, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Renate Henftling, Andreas Zinn, Matthias Bauer 0003, Wolfgang Ecker, Martin Zambaldi |
Platform-Based Testbench Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11038-11045, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Rajesh K. Gupta 0001, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi |
Formal verification - prove it or pitch it. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 710-711, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Brad L. Hutchings, Brent E. Nelson |
Unifying simulation and execution in a design environment for FPGA systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(1), pp. 201-205, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Neal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas |
Modeling and evaluation of hardware/software designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001, Copenhagen, Denmark, 2001, pp. 11-16, 2001, ACM, 1-58113-364-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
computer system modeling and simulation, hardware/software codesign, digital system design |
17 | Kazutoshi Kobayashi, Hidetoshi Onodera |
ST: PERL package for simulation and test environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 89-92, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Andrew Stone, Elias S. Manolakos |
DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 24(1), pp. 99-120, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Wei-Chung Cheng, Massoud Pedram |
Power-optimal encoding for DRAM address bus (poster session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 250-252, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Brad L. Hutchings, Brent E. Nelson |
Using general-purpose programming languages for FPGA design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 561-566, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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