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Found 23 publication records. Showing 23 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
42 | Shashidhar Thakur, D. F. Wong 0001 |
On Designing ULM-based FPGA Logic Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 3-9, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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32 | Rolf Drechsler, Wolfgang Günther 0001 |
Generation of Optimal Universal Logic Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1080-1085, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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32 | Stephen S. Yau, Calvin K. Tang |
Universal logic circuits and their modular realizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS Spring Joint Computing Conference ![In: American Federation of Information Processing Societies: AFIPS Conference Proceedings: 1968 Spring Joint Computer Conference, Atlantic City, NJ, USA, 30 April - 2 May 1968, pp. 297-305, 1968, Thomson Book Company, Washington D.C., 978-1-4503-7897-0. The full citation details ...](Pics/full.jpeg) |
1968 |
DBLP DOI BibTeX RDF |
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28 | Shashidhar Thakur, D. F. Wong 0001 |
Series-parallel functions and FPGA logic module design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(1), pp. 102-122, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
series-parallel technology mapping, tree-based technology mapping algorithm, universal logic modules, field programmable gate arrays |
28 | X. Chen, Stanley L. Hurst |
A Comparison of Universal-Logic-Module Realizations and Their Application in the Synthesis of Combinatorial and Sequential Logic Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(2), pp. 140-147, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
universal-logic-modules, Custom LSI design, function realization statistics, input-programmable gates, uncommitted-logic-arrays |
28 | Alexander Iosupovicz |
Adaptive Universal Fault-Tolerant Logic Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(10), pp. 1043-1048, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
dynamic error correction, fault-tolerant logic, tree arrays, universal logic modules, programmable logic, cellular logic, Adaptive logic |
26 | C. K. Vijayakumari, Rekha K. James, P. Mythili |
A GA Based Simple and Efficient Technique to Design Combinational Logic Circuits Using Universal Logic Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 25(7), pp. 1650074:1-1650074:22, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Shahana Thottathikkulam Kassim, Rekha K. James, K. Poulose Jacob, Sreela Sasi |
Genetic Algorithm-Based Combinational Logic Synthesis Using Universal Logic Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2007 International Conference on Embedded Systems & Applications, USA 2007, June 25-28, 2007, Las Vegas, Nevada, USA, pp. 210-215, 2007, CSREA Press, 1-60132-052-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
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26 | Wenbin Jiang |
A method for minimization design of two-level logic networks using multiplexer universal logic modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 9(1), pp. 92-96, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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22 | Andrew Zukoski, Xuebei Yang, Kartik Mohanram |
Universal logic modules based on double-gate carbon nanotube transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011, pp. 884-889, 2011, ACM, 978-1-4503-0636-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Markus Hütter |
Designing universal logic modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrovnik, Croatia, September 15-18, 2002, pp. 709-712, 2002, IEEE, 0-7803-7596-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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22 | Shashidhar Thakur, D. F. Wong 0001 |
Universal Logic Modules for Series-Parallel Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, FPGA 1996, Monterey, CA, USA, February 11-13, 1996, pp. 31-37, 1996, ACM, 0-89791-773-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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22 | A. E. A. Almaini |
Sequential Machine Implementations Using Universal Logic Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(10), pp. 951-960, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
|
22 | Sureshchander |
Comments on "Delayed Universal Logic Modules and Sequential Machine Synthesis". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(2), pp. 191, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
|
22 | Tiu Le Van, Noël van Houtte |
Delayed Universal Logic Modules and Sequential Machine Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(8), pp. 853-855, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
Accepted sequence, component machine, delayed universal logic module, distributed logic, inverse binary tree, nondeterministic automaton, reversed machine, simple synthesis, transition map, 2n-in-1 multiplexer, universal logic module, decomposition, sequential machine |
22 | Sureshchander, P. C. P. Bhatt |
A Note on Q-Universal Logic Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 23(3), pp. 319-320, 1974. The full citation details ...](Pics/full.jpeg) |
1974 |
DBLP DOI BibTeX RDF |
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22 | F. Gail Gray, Richard A. Thompson |
Reconfiguration for Repair in a Class of Universal Logic Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 23(11), pp. 1185-1194, 1974. The full citation details ...](Pics/full.jpeg) |
1974 |
DBLP DOI BibTeX RDF |
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22 | Yale N. Patt |
Optimal and Near-Optimal Universal Logic Modules with Interconnected External Terminals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 22(10), pp. 903-907, 1973. The full citation details ...](Pics/full.jpeg) |
1973 |
DBLP DOI BibTeX RDF |
|
22 | Franco P. Preparata |
Universal Logic Modules of a New Type. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 21(6), pp. 585-588, 1972. The full citation details ...](Pics/full.jpeg) |
1972 |
DBLP DOI BibTeX RDF |
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22 | Igor Aleksander |
Comments on "Universal Logic Modules and Their Applications". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 20(5), pp. 586-587, 1971. The full citation details ...](Pics/full.jpeg) |
1971 |
DBLP DOI BibTeX RDF |
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22 | Kenneth J. Thurber, Robert Orval Berg |
Universal logic modules implemented using LSI memory techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS Fall Joint Computing Conference ![In: American Federation of Information Processing Societies: Proceedings of the AFIPS '71 Fall Joint Computer Conference, November 16-18, 1971, Las Vegas, Nevada, USA, pp. 177-194, 1971, AFIPS / ACM, 978-1-4503-7910-6. The full citation details ...](Pics/full.jpeg) |
1971 |
DBLP DOI BibTeX RDF |
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22 | Stephen S. Yau, Calvin K. Tang |
Universal Logic Modules and Their Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 19(2), pp. 141-149, 1970. The full citation details ...](Pics/full.jpeg) |
1970 |
DBLP DOI BibTeX RDF |
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10 | Chip-Hong Chang, Bogdan J. Falkowski |
Reed-Muller weight and literal vectors for NPN classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 379-382, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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