Search results for "vector-reordering"

Found 12 publication records. Showing 12 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
39	S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay	Customizing pattern set for test power reduction via improved X-identification and reordering.	ISLPED	2010	DBLP DOI BibTeX RDF	don't care bits, runtime leakage power, vector reordering, x-fill, dynamic power
30	Hamidreza Hashempour, Fabrizio Lombardi	Evaluation of heuristic techniques for test vector ordering.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	test vector ordering, compression, SoC, power consumption, ATE, test data
28	Hamidreza Hashempour, Fabrizio Lombardi	A Novel Methodology for Functional Test Data Compression.	DFT	2006	DBLP DOI BibTeX RDF
28	Hamidreza Hashempour, Fabrizio Lombardi	Two dimensional reordering of functional test data for compression by ATE.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	2D reordering, column reordering, functional test data, scan test data, ATE, test data compression
23	Michael S. Hsiao, Srimat T. Chakradhar	Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	static test set compaction, vector-reordering, fault coverage curve, partitioning, ATPG
21	Minsik Cho, David Z. Pan	PEAKASO: Peak-Temperature Aware Scan-Vector Optimization.	VTS	2006	DBLP DOI BibTeX RDF
19	Hillol Maity, Kaushik Khatua, Santanu Chattopadhyay, Indranil Sengupta 0001, Girish Patankar, Parthajit Bhattacharya	A New Test Vector Reordering Technique for Low Power Combinational Circuit Testing.	ISDCS	2020	DBLP DOI BibTeX RDF
19	Tiebin Wu, Li Zhou, Hengzhu Liu	Reducing scan-shift power through scan partitioning and test vector reordering.	ICECS	2014	DBLP DOI BibTeX RDF
19	George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti 0001, Srivaths Ravi 0001	Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures.	J. Low Power Electron.	2009	DBLP DOI BibTeX RDF
19	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	Input Vector Reordering for Leakage Power Reduction in FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
19	Chandan Giri, Pradeep Kumar Choudhary, Santanu Chattopadhyay	Scan Power Reduction Through Scan Architecture Modification And Test Vector Reordering.	ATS	2007	DBLP DOI BibTeX RDF
13	Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue	A Test Decompression Scheme for Variable-Length Coding.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF