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Found 39 publication records. Showing 39 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
33 | Cheng-Yi Xiong, Jin-Wen Tian, Jian Liu 0011 |
High performance word level sequential and parallel coding methods and architectures for bit plane coding. |
Sci. China Ser. F Inf. Sci. |
2008 |
DBLP DOI BibTeX RDF |
bit plane coding, word-level sequential, multi-word parallel, high performance |
24 | María A. Trenas, Juan López, Emilio L. Zapata, Francisco Argüello |
A Configurable Architecture for the Wavelet Packet Transform. |
J. VLSI Signal Process. |
2002 |
DBLP DOI BibTeX RDF |
time-frequency tiling, word-serial, word-parallel, wavelet packets |
21 | Subhadeep Roy |
A sub-word-parallel Galois field multiply-accumulate unit for digital signal processors. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Ching-Long Su, Yin-Tsung Hwang |
Distributed arithmetic-based architectures for high speed IIR filter design. |
ICPADS |
1996 |
DBLP DOI BibTeX RDF |
high speed IIR filter, pipelining techniques, SPDM technology, parallel processing, parallel architectures, digital arithmetic, recursion, recursive filters, Distributed Arithmetic, IIR filters, DSP applications |
18 | Isaac D. Scherson, David A. Kramer, Brian D. Alleyne |
A Fine-Grain Bit-Parallel, Word-Parallel, Massively-Parallel Associative Processor. |
ICPP (1) |
1990 |
DBLP BibTeX RDF |
|
16 | Peng Yin Choo, Abram Detofsky, Ahmed Louri |
The Equivalency Processing Parallel Photonic Integrated Circuit (EP3IC), a Parallel Digital Equivalence Search Module. |
AIPR |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Ahmed Louri |
An Optical Content-Adressable Parallel Processor for Fast Searching and Retrieving. |
PARLE (1) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Andrew P. Paplinski, Nandita Bhattacharjee, Charles Greif |
Rotating Ultrasonic Signal Vectors with a Word-Parallel CORDIC Processor. |
DSD |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Phil May, Santithorn Bunchua, D. Scott Wills |
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction. |
IEEE Trans. Parallel Distributed Syst. |
2002 |
DBLP DOI BibTeX RDF |
mad postman, flit-level retransmission, Networks, energy efficient, wormhole routing, router, error control, dimension-order routing |
10 | Linyan Mei, Mohit Dandekar, Dimitrios Rodopoulos, Jeremy Constantin, Peter Debacker, Rudy Lauwereins, Marian Verhelst |
Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference. |
AICAS |
2019 |
DBLP DOI BibTeX RDF |
|
10 | Fengwei An, Keisuke Mihara, Shogo Yamazaki, Lei Chen 0001, Hans Jürgen Mattausch |
Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors. |
A-SSCC |
2015 |
DBLP DOI BibTeX RDF |
|
10 | Toshinobu Akazawa, Seiryu Sasaki, Hans Jürgen Mattausch |
Word-parallel coprocessor architecture for digital nearest Euclidean distance search. |
ESSCIRC |
2013 |
DBLP DOI BibTeX RDF |
|
10 | Yong-Suk Cho, Jae Yeon Choi |
A Hardware Implementation of Word-Parallel Bit-Serial Polynomial Basis Multiplier. |
FGIT-GDC/IESH/CGAG |
2012 |
DBLP DOI BibTeX RDF |
|
10 | Hans Jürgen Mattausch, Wataru Imafuku, Tania Ansari, Akio Kawabata, Tetsushi Koide |
Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping. |
ESSCIRC |
2010 |
DBLP DOI BibTeX RDF |
|
10 | Yusuke Oike, Makoto Ikeda, Kunihiro Asada |
A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture. |
IEEE J. Solid State Circuits |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Yuan-Hao Huang, Hsi-Pin Ma, Ming-Luen Liou, Tzi-Dar Chiueh |
A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications. |
IEEE J. Solid State Circuits |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Yusuke Oike, Makoto Ikeda, Kunihiro Asada |
A word-parallel digital associative engine with wide search range based on Manhattan distance. |
CICC |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Carlos R. Castro-Pareja, Jogikal M. Jagadeesh, Sharmila Venugopal, Raj Shekhar |
FPGA-based 3D median filtering using word-parallel systolic arrays. |
ISCAS (3) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Yusuke Oike, Makoto Ikeda, Kunihiro Asada |
A high-speed and low-voltage associative co-processor with Hamming distance ordering using word-parallel and hierarchical search architecture. |
CICC |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Hamid R. Sefiri, Majid A. Ahmadi |
Mathematical formulation of general M-D filtering by using a single building block and its novel word-parallel realization. |
ISCAS |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Dik Lun Lee |
A Word-Parallel, Bit-Serial Signature Processor for Superimposed Coding. |
ICDE |
1986 |
DBLP DOI BibTeX RDF |
|
10 | Kurt Harold Horton |
Multicomputer Interconnection Using Word Parallel Shift Register Ring Networks |
|
1984 |
RDF |
|
10 | Henry S. Warren Jr. |
Functions Realizable with Word-Parallel Logical and Two's-Complement Addition Instructions. |
Commun. ACM |
1977 |
DBLP DOI BibTeX RDF |
|
9 | David Novo, Min Li 0001, Bruno Bougard, Frederik Naessens, Liesbet Van der Perre, Francky Catthoor |
Application-driven adaptive fixed-point refinement for SDRs. |
SiPS |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Zbigniew Kokosinski, Bartlomiej Malus |
FPGA Implementations of a Parallel Associative Processor with Multi-Comparand Multi-Search Operations. |
ISPDC |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Nicholas Carriero, David Gelernter |
The S/Net's Linda Kernel. |
ACM Trans. Comput. Syst. |
1986 |
DBLP DOI BibTeX RDF |
|
7 | Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito |
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
7 | Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou |
Sub-word and reduced-width Booth multipliers for DSP applications. |
ISCAS (3) |
2002 |
DBLP DOI BibTeX RDF |
|
7 | Bojana Obrenic, Martin C. Herbordt, Arnold L. Rosenberg, Charles C. Weems |
Using Emulations to Enhance the Performance of Parallel Architectures. |
IEEE Trans. Parallel Distributed Syst. |
1999 |
DBLP DOI BibTeX RDF |
parallel algorithms, Parallel architecture, multiprocessor interconnection |
7 | Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman |
Logic Verification of Very Large Circuits Using Shark. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
7 | M. Yan, John V. McCanny, Yi Hu |
VLSI architectures for vector quantization. |
J. VLSI Signal Process. |
1995 |
DBLP DOI BibTeX RDF |
|
6 | Timothy G. Constandinou, Julius Georgiou, Chris Toumazou |
A micropower front-end interface for differential-capacitive sensor systems. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
6 | Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi |
Comb Architectures for Finite Field Multiplication in F(2^m). |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
FPGA, elliptic curve cryptography, normal basis, redundant representation, Finite field multiplier |
6 | Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen |
A new group distributed arithmetic design for the one dimensional discrete Fourier transform. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
6 | Huy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy |
Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis. |
J. VLSI Signal Process. |
1998 |
DBLP DOI BibTeX RDF |
|
6 | V. B. Fyodorov |
Bit-Parallel Selfrouting Optoelectronic Switching Fabrics for Massively Parallel Wide-Format Data Processing: Principle and Optical Architecture. |
ISPAN |
1997 |
DBLP DOI BibTeX RDF |
Free space optical interconnections, Completely connected networks, Smart pixel arrays, VCSEL technology |
6 | Mary Jane Irwin, Robert Michael Owens |
A case for digit serial VLSI signal processors. |
J. VLSI Signal Process. |
1990 |
DBLP DOI BibTeX RDF |
|
6 | Gary J. Murakami, Roy H. Campbell, Michael Faiman |
Pulsa: Non-Blocking Packet Switching with Shift-Register Rings. |
SIGCOMM |
1990 |
DBLP DOI BibTeX RDF |
|
6 | Andrew W. Appel |
Simulating digital circuits with one bit per wire. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
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