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Found 39 publication records. Showing 39 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
33 | Cheng-Yi Xiong, Jin-Wen Tian, Jian Liu 0011 |
High performance word level sequential and parallel coding methods and architectures for bit plane coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(4), pp. 337-351, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bit plane coding, word-level sequential, multi-word parallel, high performance |
24 | María A. Trenas, Juan López, Emilio L. Zapata, Francisco Argüello |
A Configurable Architecture for the Wavelet Packet Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 32(3), pp. 255-273, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
time-frequency tiling, word-serial, word-parallel, wavelet packets |
21 | Subhadeep Roy |
A sub-word-parallel Galois field multiply-accumulate unit for digital signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1626-1629, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Ching-Long Su, Yin-Tsung Hwang |
Distributed arithmetic-based architectures for high speed IIR filter design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 156-161, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high speed IIR filter, pipelining techniques, SPDM technology, parallel processing, parallel architectures, digital arithmetic, recursion, recursive filters, Distributed Arithmetic, IIR filters, DSP applications |
18 | Isaac D. Scherson, David A. Kramer, Brian D. Alleyne |
A Fine-Grain Bit-Parallel, Word-Parallel, Massively-Parallel Associative Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP (1) ![In: Proceedings of the 1990 International Conference on Parallel Processing, Urbana-Champaign, IL, USA, August 1990. Volume 1: Architecture., pp. 541-544, 1990, Pennsylvania State University Press, 0-271-00728-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
16 | Peng Yin Choo, Abram Detofsky, Ahmed Louri |
The Equivalency Processing Parallel Photonic Integrated Circuit (EP3IC), a Parallel Digital Equivalence Search Module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AIPR ![In: 29th Applied Image Pattern Recognition Workshop (AIPR 2000), 16-18 October 2000, Washington, DC, USA, Proceedings, pp. 64-70, 2000, IEEE Computer Society, 0-7695-0978-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Ahmed Louri |
An Optical Content-Adressable Parallel Processor for Fast Searching and Retrieving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (1) ![In: PARLE '91: Parallel Architectures and Languages Europe, Volume I: Parallel Architectures and Algorithms, Eindhoven, The Netherlands, June 10-13, 1991, Proceedings, pp. 338-354, 1991, Springer, 3-540-54151-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Andrew P. Paplinski, Nandita Bhattacharjee, Charles Greif |
Rotating Ultrasonic Signal Vectors with a Word-Parallel CORDIC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 254-261, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Phil May, Santithorn Bunchua, D. Scott Wills |
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 13(5), pp. 485-498, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
mad postman, flit-level retransmission, Networks, energy efficient, wormhole routing, router, error control, dimension-order routing |
10 | Linyan Mei, Mohit Dandekar, Dimitrios Rodopoulos, Jeremy Constantin, Peter Debacker, Rudy Lauwereins, Marian Verhelst |
Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICAS ![In: IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019, Hsinchu, Taiwan, March 18-20, 2019, pp. 6-10, 2019, IEEE, 978-1-5386-7884-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
10 | Fengwei An, Keisuke Mihara, Shogo Yamazaki, Lei Chen 0001, Hans Jürgen Mattausch |
Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015, pp. 1-4, 2015, IEEE, 978-1-4673-7191-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
10 | Toshinobu Akazawa, Seiryu Sasaki, Hans Jürgen Mattausch |
Word-parallel coprocessor architecture for digital nearest Euclidean distance search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference, Bucharest, Romania, September 16-20, 2013, pp. 267-270, 2013, IEEE, 978-1-4799-0643-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
10 | Yong-Suk Cho, Jae Yeon Choi |
A Hardware Implementation of Word-Parallel Bit-Serial Polynomial Basis Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FGIT-GDC/IESH/CGAG ![In: Computer Applications for Graphics, Grid Computing, and Industrial Environment - International Conferences, GDC, IESH and CGAG 2012, Held as Part of the Future Generation Information Technology Conference, FGIT 2012, Gangneug, Korea, December 16-19, 2012. Proceedings, pp. 176-181, 2012, Springer, 978-3-642-35599-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
10 | Hans Jürgen Mattausch, Wataru Imafuku, Tania Ansari, Akio Kawabata, Tetsushi Koide |
Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 36th European Solid-State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, September 13-17, 2010, pp. 538-541, 2010, IEEE, 978-1-4244-6662-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
10 | Yusuke Oike, Makoto Ikeda, Kunihiro Asada |
A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 39(8), pp. 1383-1387, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Yuan-Hao Huang, Hsi-Pin Ma, Ming-Luen Liou, Tzi-Dar Chiueh |
A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 39(1), pp. 169-183, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Yusuke Oike, Makoto Ikeda, Kunihiro Asada |
A word-parallel digital associative engine with wide search range based on Manhattan distance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC 2004, Orlando, FL, USA, October 2004, pp. 295-298, 2004, IEEE, 0-7803-8495-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Carlos R. Castro-Pareja, Jogikal M. Jagadeesh, Sharmila Venugopal, Raj Shekhar |
FPGA-based 3D median filtering using word-parallel systolic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 157-160, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Yusuke Oike, Makoto Ikeda, Kunihiro Asada |
A high-speed and low-voltage associative co-processor with Hamming distance ordering using word-parallel and hierarchical search architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003, pp. 643-646, 2003, IEEE, 0-7803-7842-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Hamid R. Sefiri, Majid A. Ahmadi |
Mathematical formulation of general M-D filtering by using a single building block and its novel word-parallel realization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 85-88, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Dik Lun Lee |
A Word-Parallel, Bit-Serial Signature Processor for Superimposed Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDE ![In: Proceedings of the Second International Conference on Data Engineering, February 5-7, 1986, Los Angeles, California, USA, pp. 352-359, 1986, IEEE Computer Society, 0-8186-0655-X. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
10 | Kurt Harold Horton |
Multicomputer Interconnection Using Word Parallel Shift Register Ring Networks ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1984 |
RDF |
|
10 | Henry S. Warren Jr. |
Functions Realizable with Word-Parallel Logical and Two's-Complement Addition Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 20(6), pp. 439-441, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
|
9 | David Novo, Min Li 0001, Bruno Bougard, Frederik Naessens, Liesbet Van der Perre, Francky Catthoor |
Application-driven adaptive fixed-point refinement for SDRs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2008, October 8-10, 2008, Washington, D.C. Metro Area, USA, pp. 245-250, 2008, IEEE, 978-1-4244-2924-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Zbigniew Kokosinski, Bartlomiej Malus |
FPGA Implementations of a Parallel Associative Processor with Multi-Comparand Multi-Search Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPDC ![In: 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 1-5 July 2008, Krakow, Poland, pp. 444-448, 2008, IEEE Computer Society, 978-0-7695-3472-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Nicholas Carriero, David Gelernter |
The S/Net's Linda Kernel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 4(2), pp. 110-129, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
7 | Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito |
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 525-528, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
7 | Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou |
Sub-word and reduced-width Booth multipliers for DSP applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 575-578, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
7 | Bojana Obrenic, Martin C. Herbordt, Arnold L. Rosenberg, Charles C. Weems |
Using Emulations to Enhance the Performance of Parallel Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 10(10), pp. 1067-1081, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
parallel algorithms, Parallel architecture, multiprocessor interconnection |
7 | Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman |
Logic Verification of Very Large Circuits Using Shark. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 310-317, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
7 | M. Yan, John V. McCanny, Yi Hu |
VLSI architectures for vector quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 10(1), pp. 5-23, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
6 | Timothy G. Constandinou, Julius Georgiou, Chris Toumazou |
A micropower front-end interface for differential-capacitive sensor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2474-2477, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
6 | Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi |
Comb Architectures for Finite Field Multiplication in F(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(7), pp. 909-916, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, elliptic curve cryptography, normal basis, redundant representation, Finite field multiplier |
6 | Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen |
A new group distributed arithmetic design for the one dimensional discrete Fourier transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 421-424, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
6 | Huy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy |
Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 18(1), pp. 25-38, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
6 | V. B. Fyodorov |
Bit-Parallel Selfrouting Optoelectronic Switching Fabrics for Massively Parallel Wide-Format Data Processing: Principle and Optical Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 479-486, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Free space optical interconnections, Completely connected networks, Smart pixel arrays, VCSEL technology |
6 | Mary Jane Irwin, Robert Michael Owens |
A case for digit serial VLSI signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 1(4), pp. 321-334, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
6 | Gary J. Murakami, Roy H. Campbell, Michael Faiman |
Pulsa: Non-Blocking Packet Switching with Shift-Register Rings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM Symposium on Communications Architectures & Protocols, SIGCOMM 1990, Philadelpia, PA, USA, September 24-27, 1990, pp. 145-155, 1990, ACM, 0-89791-405-8. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
6 | Andrew W. Appel |
Simulating digital circuits with one bit per wire. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9), pp. 987-993, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
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